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2022-12-13Merge tag 'pinctrl-v6.2-1' of ↵Linus Torvalds96-887/+3954
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "The two large chunks is the header clean-up from Andy and the Qualcomm DT bindings clean-up from Krzysztof. Each which could give rise to conflicts, but I haven't seen any. The YAML conversions happening around the device tree is the biggest item in the series and is the result of Rob Herrings ambition to autovalidate these trees against strict schemas and it is paying off in lots of bugs found and ever prettier device trees. Sooner or later the transition will be complete, Krzysztof is fixing up all of the Qualcomm stuff, which is pretty voluminous. Core changes: - minor but nice and important documentation clean-ups New drivers: - subdriver for the Qualcomm SDM670 SoC - subdriver for the Intel Moorefield SoC - trivial support for the NXP Freescale i.MXRT1170 SoC Other changes and improvements - major clean-up of the Qualcomm pin control device tree bindings by Krzysztof - major header clean-up by Andy - some immutable irqchip clean-up for the Actions Semiconductor and Nuvoton drivers - GPIO helpers for The Cypress cy8c95x0 driver - bias handling in the Mediatek MT7986 driver - remove the unused pins-are-numbered concept that never flew" * tag 'pinctrl-v6.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (231 commits) pinctrl: thunderbay: fix possible memory leak in thunderbay_build_functions() dt-bindings: pinctrl: st,stm32: Deprecate pins-are-numbered dt-bindings: pinctrl: mediatek,mt65xx: Deprecate pins-are-numbered pinctrl: stm32: Remove check for pins-are-numbered pinctrl: mediatek: common: Remove check for pins-are-numbered pinctrl: qcom: remove duplicate included header files pinctrl: sunxi: d1: Add CAN bus pinmuxes pinctrl: loongson2: Fix some const correctness pinctrl: pinconf-generic: add missing of_node_put() pinctrl: intel: Enumerate PWM device when community has a capability pwm: lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe() pwm: lpss: Allow other drivers to enable PWM LPSS pwm: lpss: Include headers we are the direct user of pwm: lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS pwm: Add a stub for devm_pwmchip_add() pinctrl: k210: call of_node_put() pinctrl: starfive: Use existing variable gpio dt-bindings: pinctrl: semtech,sx150xq: fix match patterns for 16 GPIOs matching pinconf-generic: fix style issues in pin_config_param doc pinctrl: pinctrl-loongson2: fix Kconfig dependency ...
2022-12-06pinctrl: thunderbay: fix possible memory leak in thunderbay_build_functions()Gaosheng Cui1-2/+6
The thunderbay_add_functions() will free memory of thunderbay_funcs when everything is ok, but thunderbay_funcs will not be freed when thunderbay_add_functions() fails, then there will be a memory leak, so we need to add kfree() when thunderbay_add_functions() fails to fix it. In addition, doing some cleaner works, moving kfree(funcs) from thunderbay_add_functions() to thunderbay_build_functions(). Fixes: 12422af8194d ("pinctrl: Add Intel Thunder Bay pinctrl driver") Signed-off-by: Gaosheng Cui <cuigaosheng1@huawei.com> Reviewed-by: Rafał Miłecki <rafal@milecki.pl> Link: https://lore.kernel.org/r/20221129120126.1567338-1-cuigaosheng1@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-12-03pinctrl: stm32: Remove check for pins-are-numberedBernhard Rosenkränzer1-5/+0
Remove the check for the unnecessary pins-are-numbered DeviceTree property Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221129023401.278780-3-bero@baylibre.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-12-03pinctrl: mediatek: common: Remove check for pins-are-numberedBernhard Rosenkränzer1-6/+0
Remove the check for the unnecessary pins-are-numbered Devicetree property. Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20221129023401.278780-2-bero@baylibre.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-28pinctrl: intel: Save and restore pins in "direct IRQ" modeAndy Shevchenko1-1/+26
The firmware on some systems may configure GPIO pins to be an interrupt source in so called "direct IRQ" mode. In such cases the GPIO controller driver has no idea if those pins are being used or not. At the same time, there is a known bug in the firmwares that don't restore the pin settings correctly after suspend, i.e. by an unknown reason the Rx value becomes inverted. Hence, let's save and restore the pins that are configured as GPIOs in the input mode with GPIROUTIOXAPIC bit set. Cc: stable@vger.kernel.org Reported-and-tested-by: Dale Smith <dalepsmith@gmail.com> Reported-and-tested-by: John Harris <jmharris@gmail.com> BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=214749 Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20221124222926.72326-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-28pinctrl: qcom: remove duplicate included header filesye xingchen3-3/+0
linux/seq_file.h is included more than once. Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn> Link: https://lore.kernel.org/r/202211221631577017318@zte.com.cn Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-28Merge tag 'intel-pinctrl-v6.2-2' of ↵Linus Walleij1-0/+29
git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v6.2-2 * Enable PWM feature on Intel pin control IPs The following is an automated git shortlog grouped by driver: intel: - Enumerate PWM device when community has a capability pwm: - lpss: Rename pwm_lpss_probe() --> devm_pwm_lpss_probe() - lpss: Allow other drivers to enable PWM LPSS - lpss: Include headers we are the direct user of - lpss: Rename MAX_PWMS --> LPSS_MAX_PWMS - Add a stub for devm_pwmchip_add()
2022-11-26pinctrl: sunxi: d1: Add CAN bus pinmuxesFabien Poussin1-0/+4
The D1 pin controller contains muxes for two CAN buses. While the CAN bus controllers are only documented for the T113 SoC, the pin controller is the same across all SoC variants. Signed-off-by: Fabien Poussin <fabien.poussin@gmail.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20221126191636.6673-1-samuel@sholland.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-25pinctrl: loongson2: Fix some const correctnessLinus Walleij1-2/+2
The kernel robot using sparse is complaining like this: drivers/pinctrl/pinctrl-loongson2.c:212:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void *[noderef] __iomem reg @@ (...) I think the problem is simply that the register base is defined as void * __iomem instead of void __iomem * and this is because of the way const correctness works with pointer infix order. Fix it up. I think. Reported-by: kernel test robot <lkp@intel.com> Cc: zhanghongchen <zhanghongchen@loongson.cn> Cc: Yinbo Zhu <zhuyinbo@loongson.cn> Fixes: f73f88acbc18 ("pinctrl: pinctrl-loongson2: add pinctrl driver support") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-25pinctrl: pinconf-generic: add missing of_node_put()ZhangPeng1-1/+3
of_node_put() needs to be called when jumping out of the loop, since for_each_available_child_of_node() will increase the refcount of node. Fixes: c7289500e29d ("pinctrl: pinconf-generic: scan also referenced phandle node") Signed-off-by: ZhangPeng <zhangpeng362@huawei.com> Link: https://lore.kernel.org/r/20221125070156.3535855-1-zhangpeng362@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-22pinctrl: meditatek: Startup with the IRQs disabledRicardo Ribalda1-3/+6
If the system is restarted via kexec(), the peripherals do not start with a known state. If the previous system had enabled an IRQs we will receive unexected IRQs that can lock the system. [ 28.109251] watchdog: BUG: soft lockup - CPU#0 stuck for 26s! [swapper/0:0] [ 28.109263] Modules linked in: [ 28.109273] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.15.79-14458-g4b9edf7b1ac6 #1 9f2e76613148af94acccd64c609a552fb4b4354b [ 28.109284] Hardware name: Google Elm (DT) [ 28.109290] pstate: 40400005 (nZcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 28.109298] pc : __do_softirq+0xa0/0x388 [ 28.109309] lr : __do_softirq+0x70/0x388 [ 28.109316] sp : ffffffc008003ee0 [ 28.109321] x29: ffffffc008003f00 x28: 000000000000000a x27: 0000000000000080 [ 28.109334] x26: 0000000000000001 x25: ffffffefa7b350c0 x24: ffffffefa7b47480 [ 28.109346] x23: ffffffefa7b3d000 x22: 0000000000000000 x21: ffffffefa7b0fa40 [ 28.109358] x20: ffffffefa7b005b0 x19: ffffffefa7b47480 x18: 0000000000065b6b [ 28.109370] x17: ffffffefa749c8b0 x16: 000000000000018c x15: 00000000000001b8 [ 28.109382] x14: 00000000000d3b6b x13: 0000000000000006 x12: 0000000000057e91 [ 28.109394] x11: 0000000000000000 x10: 0000000000000000 x9 : ffffffefa7b47480 [ 28.109406] x8 : 00000000000000e0 x7 : 000000000f424000 x6 : 0000000000000000 [ 28.109418] x5 : ffffffefa7dfaca0 x4 : ffffffefa7dfadf0 x3 : 000000000000000f [ 28.109429] x2 : 0000000000000000 x1 : 0000000000000100 x0 : 0000000001ac65c5 [ 28.109441] Call trace: [ 28.109447] __do_softirq+0xa0/0x388 [ 28.109454] irq_exit+0xc0/0xe0 [ 28.109464] handle_domain_irq+0x68/0x90 [ 28.109473] gic_handle_irq+0xac/0xf0 [ 28.109480] call_on_irq_stack+0x28/0x50 [ 28.109488] do_interrupt_handler+0x44/0x58 [ 28.109496] el1_interrupt+0x30/0x58 [ 28.109506] el1h_64_irq_handler+0x18/0x24 [ 28.109512] el1h_64_irq+0x7c/0x80 [ 28.109519] arch_local_irq_enable+0xc/0x18 [ 28.109529] default_idle_call+0x40/0x140 [ 28.109539] do_idle+0x108/0x290 [ 28.109547] cpu_startup_entry+0x2c/0x30 [ 28.109554] rest_init+0xe8/0xf8 [ 28.109562] arch_call_rest_init+0x18/0x24 [ 28.109571] start_kernel+0x338/0x42c [ 28.109578] __primary_switched+0xbc/0xc4 [ 28.109588] Kernel panic - not syncing: softlockup: hung tasks Signed-off-by: Ricardo Ribalda <ribalda@chromium.org> Link: https://lore.kernel.org/r/20221122-mtk-pinctrl-v1-1-bedf5655a3d2@chromium.org Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-22pinctrl: intel: Enumerate PWM device when community has a capabilityAndy Shevchenko1-0/+29
Some of the Communities may have PWM capability. In such cases, enumerate the PWM device via respective driver. A user is still responsible for setting correct pin muxing for the line that needs to output the signal. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
2022-11-22pinctrl: k210: call of_node_put()ZhangPeng1-1/+3
Since for_each_available_child_of_node() will increase the refcount of node, we need to call of_node_put() manually when breaking out of the iteration. Fixes: d4c34d09ab03 ("pinctrl: Add RISC-V Canaan Kendryte K210 FPIOA driver") Signed-off-by: ZhangPeng <zhangpeng362@huawei.com> Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com> Link: https://lore.kernel.org/r/20221122075853.2496680-1-zhangpeng362@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-22pinctrl: starfive: Use existing variable gpioGeert Uytterhoeven1-2/+2
Use the existing variable "gpio", instead of obtaining the hwirq number again. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Link: https://lore.kernel.org/r/3b6b8597792a393d0f21b8489dd933663dfd2b90.1669045778.git.geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-21pinctrl: single: Fix potential division by zeroMaxim Korotkov1-1/+1
There is a possibility of dividing by zero due to the pcs->bits_per_pin if pcs->fmask() also has a value of zero and called fls from asm-generic/bitops/builtin-fls.h or arch/x86/include/asm/bitops.h. The function pcs_probe() has the branch that assigned to fmask 0 before pcs_allocate_pin_table() was called Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 4e7e8017a80e ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules") Signed-off-by: Maxim Korotkov <korotkov.maxim.s@gmail.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20221117123034.27383-1-korotkov.maxim.s@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-21pinctrl: pinctrl-loongson2: fix Kconfig dependencyRen Zhijie1-1/+1
If CONFIG_PINCTRL_LOONGSON2=y and CONFIG_OF is not set, gcc complained about undefined reference: drivers/pinctrl/pinctrl-loongson2.o: In function `pinconf_generic_dt_node_to_map_all': pinctrl-loongson2.c:(.text+0x1c4): undefined reference to `pinconf_generic_dt_node_to_map' To fix this error, add depends on OF to config PINCTRL_LOONGSON2. Fixes: f73f88acbc18 ("pinctrl: pinctrl-loongson2: add pinctrl driver support") Signed-off-by: Ren Zhijie <renzhijie2@huawei.com> Link: https://lore.kernel.org/r/20221121132608.230645-1-renzhijie2@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-20Merge tag 'renesas-pinctrl-for-v6.2-tag1' of ↵Linus Walleij3-9/+7
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.2 - Use dynamic GPIO base on combined pincctrl/gpio controllers on SH/R-Mobile SoCs, - Miscellaneous improvements.
2022-11-18Merge tag 'intel-pinctrl-v6.2-1' of ↵Linus Walleij11-82/+1004
git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v6.2-1 * Add Intel Moorefield pin control driver * Deduplicate COMMUNITY() macro in the Intel pin control drivers * Switch Freescale GPIO driver to use fwnode instead of of_node * Miscellaneous clenups here and there The following is an automated git shortlog grouped by driver: alderlake: - Deduplicate COMMUNITY macro code cannonlake: - Deduplicate COMMUNITY macro code device property: - Introduce fwnode_device_is_compatible() helper icelake: - Deduplicate COMMUNITY macro code intel: - Add Intel Moorefield pin controller support - Use temporary variable for struct device - Use str_enable_disable() helper merrifield: - Use temporary variable for struct device qcom: - lpass-lpi: Add missed bitfield.h soc: - fsl: qe: Switch to use fwnode instead of of_node sunrisepoint: - Deduplicate COMMUNITY macro code tigerlake: - Deduplicate COMMUNITY macro code
2022-11-17pinctrl: renesas: gpio: Use dynamic GPIO base if no function GPIOsGeert Uytterhoeven1-5/+5
Since commit 502df79b860563d7 ("gpiolib: Warn on drivers still using static gpiobase allocation") in gpio/for-next, one or more warnings are printed during boot on systems where the pin controller also provides GPIO functionality: gpio gpiochip0: Static allocation of GPIO base is deprecated, use dynamic allocation. Fix this for ARM-based SH/R-Mobile SoCs by: 1. Taking into account a non-zero GPIO base in the various GPIO chip callbacks, 2. Switching to dynamic allocation of the GPIO base when support for legacy function GPIOs is not enabled. On SuperH SoCs using legacy function GPIOs, the GPIO bases of the GPIO controller and the GPIO function controller must not be changed, as all board files rely on the fixed GPIO_* and GPIO_FN_* definitions provided by the various <cpu/sh*.h> header files. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/df2cf30ac4c3cbee726799f32b727c1ebe62819c.1668000684.git.geert+renesas@glider.be
2022-11-17pinctrl: pinctrl-loongson2: add pinctrl driver supportzhanghongchen3-0/+323
The Loongson-2 SoC has a few pins that can be used as GPIOs or take multiple other functions. Add a driver for the pinmuxing. There is currently no support for GPIO pin pull-up and pull-down. Signed-off-by: zhanghongchen <zhanghongchen@loongson.cn> Co-developed-by: Yinbo Zhu <zhuyinbo@loongson.cn> Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn> Link: https://lore.kernel.org/r/20221114024942.8111-1-zhuyinbo@loongson.cn Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-15pinctrl: renesas: rzg2l: remove unnecessary check from rzg2l_dt_node_to_map()Biju Das1-2/+1
This patch removes the unnecessary check from rzg2l_dt_node_to_map() as the ret value is already negative. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20221108191309.3908415-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-15pinctrl: renesas: rzv2m: remove unnecessary check from rzv2m_dt_node_to_map()Biju Das1-2/+1
This patch removes the unnecessary check from rzv2m_dt_node_to_map() as the ret value is already negative. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20221108183223.3902097-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-15pinctrl: mediatek: Export debounce time tablesLinus Walleij1-0/+3
The kernel test robot complains that in certain combinations when building the Mediatek drivers as modules we lack some debounce table symbols, so export them. Reported-by: kernel test robot <lkp@intel.com> Fixes: e1ff91f9d230 ("pinctrl: mediatek: Fix EINT pins input debounce time configuration") Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-14pinctrl: mediatek: Fix EINT pins input debounce time configurationAngeloGioacchino Del Regno22-5/+53
The External Interrupt Controller (EINTC) on all of the supported MediaTek SoCs does support input debouncing, but not all of them index the debounce time values (DBNC_SETTING registers) the same way. Before this change, in some cases, as an example, requesting a debounce time of 16 milliseconds would mistakenly set the relative DBNC_SETTING register to 0x2, resulting in a way shorter debounce time of 500uS. To fix the aforementioned issue, define three different debounce_time arrays, reflecting the correct register index for each value and for each register index variant, and make sure that each SoC pinctrl driver uses the right one. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221111094106.18486-1-angelogioacchino.delregno@collabora.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-14pinctrl: Move for_each_maps() to namespace and hide iterator insideAndy Shevchenko2-9/+7
First of all, while for_each_maps() is private to pin control subsystem it's still better to have it put into a namespace. Besides that, users are not relying on iterator variable, so hide it inside for-loop. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20221111120048.42968-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-14pinctrl: tegra: Separate Tegra194 instancesThierry Reding3-148/+173
Tegra194 has two separate instances of the pin controller, one called AON (in the always-on domain) and another called "main". Instead of treating them as a single pin controller, split them up into two separate controllers. Doing so allows the mapping between the pinmux and GPIO controllers to be trivial identity mappings and more cleanly separates the AON from the main IP blocks. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20221104142345.1562750-4-thierry.reding@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-10pinctrl: devicetree: fix null pointer dereferencing in pinctrl_dt_to_mapZeng Heng1-0/+2
Here is the BUG report by KASAN about null pointer dereference: BUG: KASAN: null-ptr-deref in strcmp+0x2e/0x50 Read of size 1 at addr 0000000000000000 by task python3/2640 Call Trace: strcmp __of_find_property of_find_property pinctrl_dt_to_map kasprintf() would return NULL pointer when kmalloc() fail to allocate. So directly return ENOMEM, if kasprintf() return NULL pointer. Fixes: 57291ce295c0 ("pinctrl: core device tree mapping table parsing support") Signed-off-by: Zeng Heng <zengheng4@huawei.com> Link: https://lore.kernel.org/r/20221110082056.2014898-1-zengheng4@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-10pinctrl: freescale: Fix i.MXRT1050 pad namesJesse Taube1-293/+253
The pad names for the i.MXRT1050 were incorrect. Fix them. Cc: Giulio Benetti <giulio.benetti@benettiengineering.com> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Link: https://lore.kernel.org/r/20221107071511.2764628-7-Mr.Bossman075@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-10pinctrl: mediatek: add pull_type attribute for mediatek MT7986 SoCSam Shih1-0/+56
Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature") add SoC specify 'pull_type' attribute for bias configuration. This patch add pull_type attribute to pinctrl-mt7986.c, and make bias_set_combo and bias_get_combo available to mediatek MT7986 SoC. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221106080114.7426-7-linux@fw-web.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-10pinctrl: mediatek: extend pinctrl-moore to support new bias functionsSam Shih1-7/+42
Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature") introduced SoC specify 'pull_type' attribute to mtk_pinconf_bias_set_combo and mtk_pinconf_bias_get_combo, and make the functions able to support almost all Mediatek SoCs that use pinctrl-mtk-common-v2.c. This patch enables pinctrl_moore to support these functions. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221106080114.7426-6-linux@fw-web.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-10pinctrl: mediatek: fix the pinconf register offset of some pinsSam Shih1-12/+12
Correct the bias-pull-up, bias-pull-down and bias-disable register offset of mt7986 pin-42 to pin-49, in the original driver, the relative offset value was erroneously decremented by 1. Fixes: 360de6728064 ("pinctrl: mediatek: add support for MT7986 SoC") Signed-off-by: Sam Shih <sam.shih@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221106080114.7426-5-linux@fw-web.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-10pinctrl: nuvoton: wpcm450: Fix handling of inverted MFSEL bitsJonathan Neuschäfer1-3/+11
SCS3SEL and KBCCSEL use inverted logic: Whereas in other fields 0 selects the GPIO function and 1 selects the special function, in these two fields, 0 selects the special function and 1 selects the GPIO function. Adjust the code to handle this quirk. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20221105185911.1547847-3-j.neuschaefer@gmx.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-10pinctrl: nuvoton: wpcm450: Refactor MFSEL setting codeJonathan Neuschäfer1-6/+12
In preparation for the next patch, which makes the logic around setting/resetting bits in MFSEL a little more complicated, move that code to a new function Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20221105185911.1547847-2-j.neuschaefer@gmx.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-09pinctrl: mediatek: common-v2: Fix bias-disable for PULL_PU_PD_RSEL_TYPEAngeloGioacchino Del Regno1-0/+3
In pinctrl-paris we're calling the .bias_set_combo() callback when we are asked to set the pin bias to either pull up/down or pull disable. On newer platforms, this callback is mtk_pinconf_bias_set_combo(), located in pinctrl-mtk-common-v2.c: this will check the "pull type" assigned to the requested pin and in case said pin's pull type is MTK_PULL_PU_PD_RSEL_TYPE, this function will set RSEL first, PUPD last, which is fine. The issue comes when we're requesting PIN_CONFIG_BIAS_DISABLE, as this does *not* require setting RSEL but only PU_PD: in this case, the arg is MTK_DISABLE (zero), which is not a supported RSEL, due to which function mtk_pinconf_bias_set_rsel() returns a failure; because of that, mtk_pinconf_bias_set_pu_pd() is never called, hence the pin bias is never set to DISABLE. To fix this issue, add a check to mtk_pinconf_bias_set_rsel(): if we are entering that function with no pullup requested and at the same time the arg is MTK_DISABLE, this means that we're trying to disable pin bias, hence it's safe to return cleanly without ever setting any RSEL register. This makes mtk_pinconf_bias_set_combo() happy, going on with setting the PU_PD registers, which is the only action to actually take to disable bias on a pin/pingroup. Fixes: fb34a9ae383a ("pinctrl: mediatek: support rsel feature") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221104105605.33720-1-angelogioacchino.delregno@collabora.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-09pinctrl: nuvoton: wpcm450: Convert irqchip to IRQCHIP_IMMUTABLEJonathan Neuschäfer1-5/+11
Commit 6c846d026d490 ("gpio: Don't fiddle with irqchips marked as immutable") added a warning for irqchips that are not marked with IRQCHIP_IMMUTABLE. Convert the pinctrl-wpcm450 driver to an immutable irqchip. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20221031222833.201322-1-j.neuschaefer@gmx.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-08pinctrl: intel: Add Intel Moorefield pin controller supportAndy Shevchenko3-0/+928
This driver adds pinctrl support for Intel Moorefield. The IP block which is called Family-Level Interface Shim is a separate entity in SoC. The GPIO driver, which supports this pinctrl interface, will be submitted separately. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2022-11-08pinctrl: qcom: sc8280xp: Rectify UFS reset pinsAnjana Hari1-2/+2
UFS reset pin offsets are wrongly configured for SC8280XP, correcting the same for both UFS instances here. Signed-off-by: Anjana Hari <quic_ahari@quicinc.com> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Andrew Halaney <ahalaney@redhat.com> Tested-by: Andrew Halaney <ahalaney@redhat.com> # QDrive3 Link: https://lore.kernel.org/r/20221103181051.26912-1-quic_bjorande@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-08pinctrl: freescale: add pad wakeup configShenwei Wang1-0/+30
add the logic to configure the pad wakeup function via the pin_config_set handler. Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com> Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20221027130859.1444412-5-shenwei.wang@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-07pinctrl: mediatek: mt8365: use mt8365_set_clr_mode() callbackBalsam CHIHI1-0/+18
On MT8365, the SET/CLR of the mode is broken and some pin modes won't be set correctly. Use the mt8365_set_clr_mode() callback to fix the issue. Co-developed-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Balsam CHIHI <bchihi@baylibre.com> Link: https://lore.kernel.org/r/20221021084708.1109986-3-bchihi@baylibre.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-07pinctrl: mediatek: common: add mt8365_set_clr_mode() callback for broken ↵Balsam CHIHI2-1/+22
SET/CLR modes On MT8365, the SET/CLR of the mode is broken and some pin modes won't be set correctly. Add mt8365_set_clr_mode() callback for such SoCs, so that instead of using the SET/CLR register, use the main R/W register to read/update/write the modes. Co-developed-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Fabien Parent <fparent@baylibre.com> Signed-off-by: Balsam CHIHI <bchihi@baylibre.com> Link: https://lore.kernel.org/r/20221021084708.1109986-2-bchihi@baylibre.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-07pinctrl: rockchip: list all pins in a possible mux route for PX30Quentin Schulz1-0/+40
The mux routes are incomplete for the PX30. This was discovered because we had a HW design using cif-clkoutm1 with the correct pinmux in the Device Tree but the clock would still not work. There are actually two muxing required: the pin muxing (performed by the usual Device Tree pinctrl nodes) and the "function" muxing (m0 vs m1; performed by the mux routing inside the driver). The pin muxing was correct but the function muxing was not. This adds the missing pins and their configuration for the mux routes that are already specified in the driver. Note that there are some "conflicts": it is possible *in Device Tree* to (attempt to) mux the pins for e.g. clkoutm1 and clkinm0 at the same time but this is actually not possible in hardware (because both share the same bit for the function muxing). Since it is an impossible hardware design, it is not deemed necessary to prevent the user from attempting to "misconfigure" the pins/functions. Fixes: 87065ca9b8e5 ("pinctrl: rockchip: Add pinctrl support for PX30") Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Link: https://lore.kernel.org/r/20221017-upstream-px30-cif-clkoutm1-v1-0-4ea1389237f7@theobroma-systems.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-11-03pinctrl: merrifield: Use temporary variable for struct deviceAndy Shevchenko1-8/+7
Use temporary variable for struct device to make code neater. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-11-03pinctrl: intel: Use temporary variable for struct deviceAndy Shevchenko1-11/+12
Use temporary variable for struct device to make code neater. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-11-01pinctrl: qcom: lpass-lpi: Add missed bitfield.hAndy Shevchenko1-0/+1
Previously the cleanup change dropped the bitfield.h from the pinctrl-lpass-lpi.h, since it's not used there, but forgot to re-instantiate it in the C-file, where users are located. Fix this by adding missed bitfield.h to the C-file. Fixes: aa9430f8a6de ("pinctrl: qcom: Add missing header(s)") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2022-10-26pinctrl: intel: Use str_enable_disable() helperAndy Shevchenko1-1/+2
Use str_enable_disable() helper instead of open coding the same. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2022-10-26pinctrl: tigerlake: Deduplicate COMMUNITY macro codeAndy Shevchenko1-14/+14
Define a common COMMUNITY macro and supply a variant to it. This removes some verbosity in macros. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-10-26pinctrl: sunrisepoint: Deduplicate COMMUNITY macro codeAndy Shevchenko1-16/+16
Define a common COMMUNITY macro and supply a variant to it. This removes some verbosity in macros. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-10-26pinctrl: icelake: Deduplicate COMMUNITY macro codeAndy Shevchenko1-4/+4
Define a common COMMUNITY macro and supply a variant to it. This removes some verbosity in macros. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-10-26pinctrl: cannonlake: Deduplicate COMMUNITY macro codeAndy Shevchenko1-4/+4
Define a common COMMUNITY macro and supply a variant to it. This removes some verbosity in macros. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2022-10-26pinctrl: alderlake: Deduplicate COMMUNITY macro codeAndy Shevchenko1-24/+16
Define a common COMMUNITY macro and supply a variant to it. This removes some verbosity in macros. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-26 08:37:40 +0000