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2017-11-30pinctrl: sunxi: Disable strict mode for H5 driverAndre Przywara1-2/+4
All of the H5 boards in the kernel reference the MMC0 CD pin twice in their DT, so strict mode will make the MMC driver fail to load. To keep existing DTs working, disable strict mode in the H5 driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reported-by: Chris Obbard <obbardc@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-30pinctrl: sunxi: Fix A64 UART mux valueAndre Przywara1-1/+1
To use pin PF4 as the RX signal of UART0, we have to write 0b011 into the respective pin controller register. Fix the wrong value we had in our table so far. Fixes: 96851d391d02 ("drivers: pinctrl: add driver for Allwinner A64 SoC") Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-30pinctrl: sunxi: Fix A80 interrupt pin bankAndre Przywara1-3/+3
On the A80 the pins on port B can trigger interrupts, and those are assigned to the second interrupt bank. Having two pins assigned to the same interrupt bank/pin combination does not look healthy (instead more like a copy&paste bug from pins PA14-PA16), so fix the interrupt bank for pins PB14-PB16, which is actually 1. I don't have any A80 board, so could not test this. Fixes: d5e9fb31baa2 ("pinctrl: sunxi: Add A80 pinctrl muxing options") Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-30pinctrl: gemini: Fix usage of 3512 groupsLinus Walleij1-1/+1
The pin config lookup function was still hardcoding the 3516 pin set, which is obviously wrong. Use the pointer in the state container. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-29pinctrl: armada-37xx: Fix direction_output() callback behaviorGregory CLEMENT1-2/+11
The direction_output callback of the gpio_chip structure is supposed to set the output direction but also to set the value of the gpio. For the armada-37xx driver this callback acted as the gpio_set_direction callback for the pinctrl. This patch fixes the behavior of the direction_output callback by also applying the value received as parameter. Cc: stable@vger.kernel.org Fixes: 5715092a458c ("pinctrl: armada-37xx: Add gpio support") Reported-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-29pinctrl: denverton: Fix UART2 RTS pin modeAndy Shevchenko1-1/+1
UART2 RTS is mode 2 of the pin. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-16Merge tag 'pinctrl-v4.15-1' of ↵Linus Torvalds67-3100/+6093
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.15 kernel cycle: Core: - The pin control Kconfig entry PINCTRL is now turned into a menuconfig option. This obviously has the implication of making the subsystem menu visible in menuconfig. This is happening because of two things: (a) Intel have started to deploy and depend on pin controllers in a way that is affecting users directly. This happens on the highly integrated laptop chipsets named after geographical places: baytrail, broxton, cannonlake, cedarfork, cherryview, denverton, geminilake, lewisburg, merrifield, sunrisepoint... It started a while back and now it is ever more evident that this is crucial infrastructure for x86 laptops and not an embedded obscurity anymore. Users need to be aware. (b) Pin control expanders on I2C and SPI that are arch-agnostic. Currently Semtech SX150X and Microchip MCP28x08 but more are expected. Users will have to be able to configure these in directly for their set-up. - Just go and select GPIOLIB now that we made sure that GPIOLIB is a very vanilla subsystem. Do not depend on it, if we need it, select it. - Exposing the pin control subsystem in menuconfig uncovered a bunch of obscure bugs that are now hopefully fixed, all more or less pertaining to Blackfin. - Unified namespace for cross-calls between pin control and GPIO. - New support for clock skew/delay generic DT bindings and generic pin config options for this. - Minor documentation improvements. Various: - The Renesas SH-PFC pin controller has evolved a lot. It seems Renesas are churning out new SoCs by the minute. - A bunch of non-critical fixes for the Rockchip driver. - Improve the use of library functions instead of open coding. - Support the MCP28018 variant in the MCP28x08 driver. - Static constifying" * tag 'pinctrl-v4.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (91 commits) pinctrl: gemini: Fix missing pad descriptions pinctrl: Add some depends on HAS_IOMEM pinctrl: samsung/s3c24xx: add CONFIG_OF dependency pinctrl: gemini: Fix GMAC groups pinctrl: qcom: spmi-gpio: Add pmi8994 gpio support pinctrl: ti-iodelay: remove redundant unused variable dev pinctrl: max77620: Use common error handling code in max77620_pinconf_set() pinctrl: gemini: Implement clock skew/delay config pinctrl: gemini: Use generic DT parser pinctrl: Add skew-delay pin config and bindings pinctrl: armada-37xx: Add edge both type gpio irq support pinctrl: uniphier: remove eMMC hardware reset pin-mux pinctrl: rockchip: Add iomux-route switching support for rk3288 pinctrl: intel: Add Intel Cedar Fork PCH pin controller support pinctrl: intel: Make offset to interrupt status register configurable pinctrl: sunxi: Enforce the strict mode by default pinctrl: sunxi: Disable strict mode for old pinctrl drivers pinctrl: sunxi: Introduce the strict flag pinctrl: sh-pfc: Save/restore registers for PSCI system suspend pinctrl: sh-pfc: r8a7796: Use generic IOCTRL register description ...
2017-11-14Merge tag 'gpio-v4.15-1' of ↵Linus Torvalds20-29/+27
ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio Pull GPIO updates from Linus Walleij: "This is the bulk of GPIO changes for the v4.15 kernel cycle: Core: - Fix the semantics of raw GPIO to actually be raw. No inversion semantics as before, but also no open draining, and allow the raw operations to affect lines used for interrupts as the caller supposedly knows what they are doing if they are getting the big hammer. - Rewrote the __inner_function() notation calls to names that make more sense. I just find this kind of code disturbing. - Drop the .irq_base() field from the gpiochip since now all IRQs are mapped dynamically. This is nice. - Support for .get_multiple() in the core driver API. This allows us to read several GPIO lines with a single register read. This has high value for some usecases: it can be used to create oscilloscopes and signal analyzers and other things that rely on reading several lines at exactly the same instant. Also a generally nice optimization. This uses the new assign_bit() macro from the bitops lib that was ACKed by Andrew Morton and is implemented for two drivers, one of them being the generic MMIO driver so everyone using that will be able to benefit from this. - Do not allow requests of Open Drain and Open Source setting of a GPIO line simultaneously. If the hardware actually supports enabling both at the same time the electrical result would be disastrous. - A new interrupt chip core helper. This will be helpful to deal with "banked" GPIOs, which means GPIO controllers with several logical blocks of GPIO inside them. This is several gpiochips per device in the device model, in contrast to the case when there is a 1-to-1 relationship between a device and a gpiochip. New drivers: - Maxim MAX3191x industrial serializer, a very interesting piece of professional I/O hardware. - Uniphier GPIO driver. This is the GPIO block from the recent Socionext (ex Fujitsu and Panasonic) platform. - Tegra 186 driver. This is based on the new banked GPIO infrastructure. Other improvements: - Some documentation improvements. - Wakeup support for the DesignWare DWAPB GPIO controller. - Reset line support on the DesignWare DWAPB GPIO controller. - Several non-critical bug fixes and improvements for the Broadcom BRCMSTB driver. - Misc non-critical bug fixes like exotic errorpaths, removal of dead code etc. - Explicit comments on fall-through switch() statements" * tag 'gpio-v4.15-1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (65 commits) gpio: tegra186: Remove tegra186_gpio_lock_class gpio: rcar: Add r8a77995 (R-Car D3) support pinctrl: bcm2835: Fix some merge fallout gpio: Fix undefined lock_dep_class gpio: Automatically add lockdep keys gpio: Introduce struct gpio_irq_chip.first gpio: Disambiguate struct gpio_irq_chip.nested gpio: Add Tegra186 support gpio: Export gpiochip_irq_{map,unmap}() gpio: Implement tighter IRQ chip integration gpio: Move lock_key into struct gpio_irq_chip gpio: Move irq_valid_mask into struct gpio_irq_chip gpio: Move irq_nested into struct gpio_irq_chip gpio: Move irq_chained_parent to struct gpio_irq_chip gpio: Move irq_default_type to struct gpio_irq_chip gpio: Move irq_handler to struct gpio_irq_chip gpio: Move irqdomain into struct gpio_irq_chip gpio: Move irqchip into struct gpio_irq_chip gpio: Introduce struct gpio_irq_chip pinctrl: armada-37xx: remove unused variable ...
2017-11-13Merge branch 'irq-core-for-linus' of ↵Linus Torvalds1-2/+3
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq core updates from Thomas Gleixner: "A rather large update for the interrupt core code and the irq chip drivers: - Add a new bitmap matrix allocator and supporting changes, which is used to replace the x86 vector allocator which comes with separate pull request. This allows to replace the convoluted nested loop allocation function in x86 with a facility which supports the recently added property of managed interrupts proper and allows to switch to a best effort vector reservation scheme, which addresses problems with vector exhaustion. - A large update to the ARM GIC-V3-ITS driver adding support for range selectors. - New interrupt controllers: - Meson and Meson8 GPIO - BCM7271 L2 - Socionext EXIU If you expected that this will stop at some point, I have to disappoint you. There are new ones posted already. Sigh! - STM32 interrupt controller support for new platforms. - A pile of fixes, cleanups and updates to the MIPS GIC driver - The usual small fixes, cleanups and updates all over the place. Most visible one is to move the irq chip drivers Kconfig switches into a separate Kconfig menu" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (70 commits) genirq: Fix type of shifting literal 1 in __setup_irq() irqdomain: Drop pointless NULL check in virq_debug_show_one genirq/proc: Return proper error code when irq_set_affinity() fails irq/work: Use llist_for_each_entry_safe irqchip: mips-gic: Print warning if inherited GIC base is used irqchip/mips-gic: Add pr_fmt and reword pr_* messages irqchip/stm32: Move the wakeup on interrupt mask irqchip/stm32: Fix initial values irqchip/stm32: Add stm32h7 support dt-bindings/interrupt-controllers: Add compatible string for stm32h7 irqchip/stm32: Add multi-bank management irqchip/stm32: Select GENERIC_IRQ_CHIP irqchip/exiu: Add support for Socionext Synquacer EXIU controller dt-bindings: Add description of Socionext EXIU interrupt controller irqchip/gic-v3-its: Fix VPE activate callback return value irqchip: mips-gic: Make IPI bitmaps static irqchip: mips-gic: Share register writes in gic_set_type() irqchip: mips-gic: Remove gic_vpes variable irqchip: mips-gic: Use num_possible_cpus() to reserve IPIs irqchip: mips-gic: Configure EIC when CPUs come online ...
2017-11-13pinctrl: gemini: Fix missing pad descriptionsLinus Walleij1-0/+2
A pretty clever static checker found a bug in my patch: I added more bits to a bitmask but didn't extend the array indexed to the same bitmask. Fixes: 756a024f3983 ("pinctrl: gemini: Fix GMAC groups") Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-13pinctrl: Add some depends on HAS_IOMEMLinus Walleij1-0/+2
Some compilation fallout from UM Linux (which does not have IOMEM) makes it necessary to depend on HAS_IOMEM for drivers that doesn't have other factors restricting their selection. Cc: Phil Reid <preid@electromag.com.au> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Reported-by: R. Daneel Olivaw <kbuild-all@01.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-10pinctrl: samsung/s3c24xx: add CONFIG_OF dependencyArnd Bergmann1-1/+1
The driver fails to build without CONFIG_OF: drivers/pinctrl/samsung/pinctrl-samsung.c: In function 'samsung_gpiolib_register': drivers/pinctrl/samsung/pinctrl-samsung.c:936:5: error: 'struct gpio_chip' has no member named 'of_node' This configuration is now possible since we can now select the PINCTRL subsystem on S3C24xx machines other than the device tree based ones. Fixes: d219b924611a ("pinctrl: change Kconfig PINCTRL variable to a menuconfig") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-09Merge branch 'gpio-irqchip-rework' of /home/linus/linux-gpio into develLinus Walleij20-29/+27
2017-11-09pinctrl: bcm2835: Fix some merge falloutLinus Walleij1-1/+1
Fixing a small merge problem in BCM2835 related to the new irqchip code. Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08gpio: Move irq_valid_mask into struct gpio_irq_chipThierry Reding2-4/+4
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08gpio: Move irqdomain into struct gpio_irq_chipThierry Reding20-22/+22
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08pinctrl: gemini: Fix GMAC groupsLinus Walleij1-25/+54
The GMII groups need to be split across GMAC0 and GMAC1 since GMAC0 is always available but GMAC1 masks GPIO2 lines 0-7 so we might want just one interface out. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08pinctrl: qcom: spmi-gpio: Add pmi8994 gpio supportRajendra Nayak1-0/+1
Update the binding and driver for pmi8994-gpios Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08pinctrl: ti-iodelay: remove redundant unused variable devColin Ian King1-4/+0
The pointer dev is being assigned but is never used, hence it is redundant and can be removed. Cleans up clang warnings: drivers/pinctrl/ti/pinctrl-ti-iodelay.c:582:2: warning: Value stored to 'dev' is never read drivers/pinctrl/ti/pinctrl-ti-iodelay.c:701:2: warning: Value stored to 'dev' is never read Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08pinctrl: max77620: Use common error handling code in max77620_pinconf_set()Markus Elfring1-10/+11
* Add a jump target so that a specific error message is stored only once at the end of this function implementation. * Replace two calls of the function "dev_err" by goto statements. * Adjust two condition checks. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08pinctrl: gemini: Implement clock skew/delay configLinus Walleij1-4/+174
This enabled pin config on the Gemini driver and implements pin skew/delay so that the ethernet pins clocking can be properly configured. Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08pinctrl: gemini: Use generic DT parserLinus Walleij2-62/+5
We can just use the generic Device Tree parser code in this driver and save some code. Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08pinctrl: Add skew-delay pin config and bindingsLinus Walleij1-0/+2
Some pin controllers (such as the Gemini) can control the expected clock skew and output delay on certain pins with a sub-nanosecond granularity. This is typically done by shunting in a number of double inverters in front of or behind the pin. Make it possible to configure this with a generic binding. Cc: devicetree@vger.kernel.org Acked-by: Rob Herring <robh@kernel.org> Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-03pinctrl: armada-37xx: remove unused variableArnd Bergmann1-2/+0
A cleanup left behind a temporary variable that is now unused: drivers/pinctrl/mvebu/pinctrl-armada-37xx.c: In function 'armada_37xx_irq_startup': drivers/pinctrl/mvebu/pinctrl-armada-37xx.c:693:20: error: unused variable 'chip' [-Werror=unused-variable] This removes the declarations as well. Fixes: 3ee9e605caea ("pinctrl: armada-37xx: Stop using struct gpio_chip.irq_base") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-02Merge tag 'spdx_identifiers-4.14-rc8' of ↵Linus Torvalds25-0/+25
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull initial SPDX identifiers from Greg KH: "License cleanup: add SPDX license identifiers to some files Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>" * tag 'spdx_identifiers-4.14-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: License cleanup: add SPDX license identifier to uapi header files with a license License cleanup: add SPDX license identifier to uapi header files with no license License cleanup: add SPDX GPL-2.0 license identifier to files with no license
2017-11-02License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman25-0/+25
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-10-31pinctrl: armada-37xx: Add edge both type gpio irq supportKen Ma1-0/+64
Current edge both type gpio irqs which need to swap polarity in each interrupt are not supported, this patch adds edge both type gpio irq support. Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-10-31pinctrl: uniphier: remove eMMC hardware reset pin-muxMasahiro Yamada3-6/+6
This is handled by the mmc-pwrseq-emmc driver, which controls an eMMC hardware reset via a GPIO line. Remove it from the function pin-mux settings. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-10-31pinctrl: rockchip: Add iomux-route switching support for rk3288Heiko Stuebner1-0/+20
The rk3288 also has one function that can be routed to one of two pins, the hdmi cec functionality can use either gpio7c0 or gpio7c7. So add the route switching support for it. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Hans Verkuil <hans.verkuil@cisco.com> Reviewed-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-10-31pinctrl: intel: Add Intel Cedar Fork PCH pin controller supportMika Westerberg3-0/+384
Intel Cedar Fork PCH is the successor of Intel Denverton PCH but it is based on the newer GPIO/pinctrl hardware block. Add a new pinctrl/GPIO driver to support it. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-10-31pinctrl: intel: Make offset to interrupt status register configurableMika Westerberg2-8/+15
Some GPIO blocks have the interrupt status (GPI_IS) offset different than it normally is, so make it configurable. If no offset is specified we use the default. While there remove two unused constants from the core driver. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-10-31pinctrl: sunxi: Enforce the strict mode by defaultMaxime Ripard1-0/+1
The strict mode should always have been enabled on our driver, and leaving it unchecked just makes it harder to find a migration path as time passes. Let's enable it by default now so that hopefully the new SoCs should be safe. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-10-31pinctrl: sunxi: Disable strict mode for old pinctrl driversMaxime Ripard11-2/+13
Old pinctrl drivers will need to disable strict mode for various reasons, among which: - Some DT will still have a pinctrl group for each GPIO used, which will be rejected by pin_request. While we could remove those nodes, we still have to deal with old DTs. - Some GPIOs on these boards need to have their pin configuration changed (for bias or current), and there's no clear migration path Let's disable the strict mode on those SoCs so that there's no breakage. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-10-31pinctrl: sunxi: Introduce the strict flagMaxime Ripard2-1/+12
Our pinctrl device should have had strict set all along. However, it wasn't the case, and most of our old device trees also have a pinctrl group in addition to the GPIOs properties, which mean that we can't really turn it on now. All our new SoCs don't have that group, so we should still enable that mode on the newer one though. In order to enable it by default, add a flag that will allow to disable that mode that should be set by pinctrl drivers that cannot be migrated. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-10-20Merge tag 'sh-pfc-for-v4.15-tag2' of ↵Linus Walleij11-977/+2464
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.15 (take two) - Add Audio, HSCIF, I2C, and INTC-EX pin groups on R-Car H3 ES2.0, - Add Audio and PWM pin groups on R-Car D3, - Add support for RZ/A1M and RZ/A1L, - Add INTC-EX pin groups on R-Car M3-W, - Add SDHI voltage switching on RZ/G1E, - Make bias control and IOCTRL support more generic, - Add suspend/resume support for R-Car Gen3, - Small fixes and cleanups.
2017-10-20pinctrl: sh-pfc: Save/restore registers for PSCI system suspendGeert Uytterhoeven2-0/+98
During PSCI system suspend, R-Car Gen3 SoCs are powered down, and their pinctrl register state is lost. Note that as the boot loader skips most initialization after system resume, pinctrl register state differs from the state encountered during normal system boot, too. To fix this, save all GPIO and peripheral function select, module select, drive strength control, bias, and other I/O control registers during system suspend, and restore them during system resume. Note that to avoid overhead on platforms not needing it, the suspend/resume code has a build time dependency on sleep and PSCI support, and a runtime dependency on PSCI. Inspired by a patch in the BSP by Hien Dang. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-10-20pinctrl: sh-pfc: r8a7796: Use generic IOCTRL register descriptionGeert Uytterhoeven1-1/+11
Move R-Car M3-W I/O voltage support over to the generic way to describe IOCTRL registers, which will be needed for suspend/resume support. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-10-20pinctrl: sh-pfc: r8a7795: Use generic IOCTRL register descriptionGeert Uytterhoeven1-1/+11
Move R-Car H3 ES2.0 I/O voltage support over to the generic way to describe IOCTRL registers, which will be needed for suspend/resume support. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-10-20pinctrl: sh-pfc: r8a7795-es1: Use generic IOCTRL register descriptionGeert Uytterhoeven1-1/+11
Move R-Car H3 ES1.x I/O voltage support over to the generic way to describe IOCTRL registers, which will be needed for suspend/resume support. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-10-20pinctrl: sh-pfc: Add generic IOCTRL register descriptionGeert Uytterhoeven1-0/+5
Add a generic way to describe IOCTRL registers (for e.g. SD I/O voltage and time delay control), like is already done for config, drive, and bias registers. This makes the sh-pfc core code aware of these registers, which will ease introducing suspend/resume support later. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-10-20pinctrl: sh-pfc: Remove obsolete sh_pfc_pin_to_bias_info()Geert Uytterhoeven3-24/+0
All users of sh_pfc_pin_to_bias_info() and the related data structures have been converted to sh_pfc_pin_to_bias_reg(), so those can be removed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2017-10-20pinctrl: sh-pfc: r8a7778: Use generic bias register descriptionGeert Uytterhoeven1-181/+222
Move R-Car M1A bias support over to the generic way to describe bias registers. As the new description is more compact, this decreases kernel size by ca. 148 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-10-20pinctrl: sh-pfc: r8a7796: Use generic bias register descriptionGeert Uytterhoeven1-241/+258
Move R-Car M3-W bias support over to the generic way to describe bias registers, which will be needed for suspend/resume support. As the new description is more compact, this decreases kernel size by ca. 304 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-10-20pinctrl: sh-pfc: r8a7795: Use generic bias register descriptionGeert Uytterhoeven1-241/+258
Move R-Car H3 ES2.0 bias support over to the generic way to describe bias registers, which will be needed for suspend/resume support. As the new description is more compact, this decreases kernel size by ca. 308 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-10-20pinctrl: sh-pfc: r8a7795-es1: Use generic bias register descriptionGeert Uytterhoeven1-241/+258
Move R-Car H3 ES1.x bias support over to the generic way to describe bias registers, which will be needed for suspend/resume support. As the new description is more compact, this decreases kernel size by ca. 304 bytes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2017-10-20pinctrl: sh-pfc: Add sh_pfc_pin_to_bias_reg() helperGeert Uytterhoeven2-0/+23
Add a helper to look up bias registers and bit number for a specific pin, using the generic bias register description. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-10-20pinctrl: sh-pfc: Add generic bias register descriptionGeert Uytterhoeven1-0/+12
Add a generic way to describe bias registers (for pull-up/down control), like is already done for config and drive registers. This makes the sh-pfc core code aware of these registers, which will ease introducing suspend/resume support later. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2017-10-20pinctrl: sh-pfc: Drop width parameter of sh_pfc_{read,write}_reg()Geert Uytterhoeven6-31/+30
On modern Renesas SoCs, all PFC registers are 32-bit, and all callers of sh_pfc_{read,write}_reg() already operate on 32-bit registers only. Hence make the 32-bit width implicit, and rename the functions to sh_pfc_{read,write}() to shorten lines. All accesses to 8-bit or 16-bit registers are still done using sh_pfc_{read,write}_raw_reg(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2017-10-20pinctrl: sh-pfc: Remove matching on plain sh-pfc platform deviceGeert Uytterhoeven1-6/+1
As of commit 8682b3c522c639f3 ("sh-pfc: Remove platform device registration"), plain "sh-pfc" platform devices are no longer created. Hence remove their match entry, and the now obsolete checks for missing device IDs and driver data. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2017-10-19pinctrl: armada-37xx: Stop using struct gpio_chip.irq_baseThierry Reding1-2/+2
The Armada 37xx driver always initializes the IRQ base to 0, hence the subtraction is a no-op. Remove the subtraction and thereby the last user of struct gpio_chip's .irq_base field. Note that this was also actually a bug and only worked because of the above assumption. If the IRQ base had been dynamically allocated, the subtraction would've caused the wrong mask to be generated since the struct irq_data.hwirq field is an index local to the IRQ domain. As a result, it should now be safe to also allocate this chip's IRQ base dynamically, unless there are consumers left that refer to the IRQs by their global number. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>