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path: root/drivers/pinctrl/sh-pfc
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2014-03-05pinctrl: sh-pfc: r8a7791: SD1_CLK fixMagnus Damm1-2/+4
Fix the SD1_CLK handling for r8a7791. Without this patch it is impossible to request all pins needed for SDHI1 on the Koelsch board. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-21Merge tag 'pinctrl-v3.14-1' of ↵Linus Torvalds24-232/+1438
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull bulk pin control changes from Linus Walleij: "This has been queued and tested for a while. Lots of action here, like in the GPIO tree, embedded stuff like this is really hot now it seems. Details in the signed tag. I'm especially happy about the Qualcomm driver as it is used in such a huge subset of mobile handsets out there, and these platforms in general need better upstream support - New driver for the Qualcomm TLMM pin controller and its msm8x74 subdriver. - New driver for the Broadcom Capri BCM281xx SoC. - New subdriver for the imx25 pin controller. - New subdriver for the Tegra124 pin controller. - Lock GPIO lines as IRQs for select combined pin control and GPIO drivers for baytrail and sirf. - Some semi-big refactorings and extenstions to the sirf driver. - Lots of patching, cleanup and fixing in the Renesas "PFC" driver and associated subdrivers as usual. It is settling down a little bit now it seems. - Minor fixes and incremental updates here and there as usual" * tag 'pinctrl-v3.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits) pinctrl: sunxi: Honor GPIO output initial vaules pinctrl: capri: add dependency on OF ARM: bcm11351: Enable pinctrl for Broadcom Capri SoCs ARM: pinctrl: Add Broadcom Capri pinctrl driver pinctrl: Add pinctrl binding for Broadcom Capri SoCs pinctrl: Add void * to pinctrl_pin_desc pinctrl: st: Fix a typo in probe pinctrl: Fix some typos and grammar issues in the documentation pinctrl: sirf: lock IRQs when starting them pinctrl: sirf: put gpio interrupt pin into input status automatically pinctrl: sirf: use only one irq_domain for the whole device node pinctrl: single: fix infinite loop caused by bad mask pinctrl: single: fix pcs_disable with bits_per_mux pinctrl: single: fix DT bindings documentation pinctrl: as3722: Set pin to output mode for some function pinctrl: sirf: add pin group for USP0 with only RX or TX frame sync pinctrl: sirf: fix the pins of sdmmc5 connected with TriG pinctrl: sirf: add lost usp1_uart_nostreamctrl group for atlas6 pinctrl: sunxi: Add Allwinner A20 clock output pin functions pinctrl/lantiq: fix typo ...
2014-01-07pinctrl: sh-pfc: r8a7791: Add I2C pinsValentine Barshak1-0/+196
This adds I2C[0-4] pinmux support to R8A7791 SoC. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-07pinctrl: sh-pfc: r8a7791: Add VIN pinsValentine Barshak1-0/+360
This adds VIN[0-2] pinmux support to r8a7791 SoC. VIN1 B mirror is also added along with the primary configuration since it's the only one that provides access to all 24 data bits on VIN1. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-07pinctrl: sh-pfc: r8a7791: Group USB PWEN and OVC pins togetherValentine Barshak1-28/+12
This groups USB PWEN and OVC pins together on R8A7791 SoC, the same way it's done on R8A7790, since both are needed for a USB device. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-01-07pinctrl: sh-pfc: r8a7790: Fix vsync value in the vin3_sync_mux arrayValentine Barshak1-1/+1
This fixes a typo in the vin3_sync_mux array (s/VI2/VI3/). Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-20pinctrl: sh-pfc: ARM: Constify pins and cfg_regs arraysLaurent Pinchart8-11/+11
The arrays are never modified, declare them as const. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-20pinctrl: sh-pfc: sh: Constify pins and cfg_regs arraysLaurent Pinchart12-12/+12
The arrays are never modified, declare them as const. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-20pinctrl: sh-pfc: Constify IRQ GPIOs arraysLaurent Pinchart2-3/+3
The arrays are never modified, make them const. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-20pinctrl: sh-pfc: Constify enum_ids and var_field_width compound literalsLaurent Pinchart1-4/+5
The enum_ids and var_field_width fields of struct pinmux_data_reg and pinmux_cfg_reg are initialized using compound literals. Cast them to const to store them in .rodata. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12sh-pfc: Support GPIO to IRQ mapping specified IRQ resourcesLaurent Pinchart3-17/+68
On non-DT platforms IRQ controllers associated with the GPIOs have a fixed IRQ base value known at compile time. The sh-pfc driver translates GPIO number to IRQ numbers using a hardcoded table. This mechanism breaks on DT platforms, as the IRQ base values are dynamic in that case. Fix this by specifying IRQs associated with GPIOs in IRQ resources, populated automatically from the device tree. When IRQ resources are specified the driver requires one IRQ resource per GPIO able to generate an interrupt, and uses the translation table to compute the IRQ resource offset instead of the IRQ number. Cc: devicetree@vger.kernel.org Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12sh-pfc: Rename sh_pfc window field to windowsLaurent Pinchart7-20/+21
There's more than one window, name the field windows. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12sh-pfc: sh73a0: Sort IRQ entries by IRQ numberLaurent Pinchart1-24/+23
This makes catching duplicate entries easier. Merge the two IRQ9 entries found after sorting. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12sh-pfc: sh73a0: Add missing IRQ15Laurent Pinchart1-0/+1
The external IRQ15 input multiplexed on GPIO 0 is missing. Add it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12sh-pfc: Terminate gpios array by -1Laurent Pinchart2-4/+4
0 is a valid GPIO value, use -1 to terminate the gpios array in IRQ lists. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-12sh-pfc: Turn unsigned indices into unsigned intLaurent Pinchart2-5/+5
Some indices take positive values only, make them unsigned. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-10pinctrl: sh-pfc: pfc-r8a7790: Add VIN2 and VIN3 pinsValentine Barshak1-0/+168
There are VIN2 and VIN3 channels available on the R8A7790 SoC. VIN2 supports 4/8/16/18/24-bit data, while VIN3 supports 8-bit. Add both here, covering all possible data pin configurations. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2013-12-10pinctrl: sh-pfc: pfc-r8a7790: Add missing VIN1 pinsValentine Barshak1-8/+104
Both VIN0 and VIN1 channels support identical input interfaces. Add missing VIN1 pins here and organize them in the same pin groups as VIN0. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2013-12-10pinctrl: sh-pfc: pfc-r8a7790: Reorganize VIN0 data pinsValentine Barshak1-30/+95
This reorganizes and renames VIN0 data pin groups to cover all possible configurations. There's total of eight data pin groups, one per each configuration. Most of the groups share the same pin/mux array. Only the 18-bit configuration needs a separate pin/mux array since in combines interleaved data pins. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2013-12-10pinctrl: sh-pfc: pfc-r8a7790: Group VIN0 HSYNC and VSYNC togetherValentine Barshak1-12/+6
This groups VIN0 HSYNC and VSYNC pins together since one cannot be used without another. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2013-12-10pinctrl: sh-pfc: pfc-r8a7790: Rename VIN pin groupsValentine Barshak1-16/+16
This drops superfluous "signal" word from the pin group names and renames data_enable group to clkenb as in the h/w manual. Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2013-12-10sh-pfc: r8a7791: Fix msiof groups to follow GROUPTakashi Yoshii1-6/+15
SH_PFC_PIN_GROUP(), pins[], mux[], defines clk, sync, ss1, ss2, rx, tx But, msiof?_groups[] defines clk, ctrl, data Fix msiof[012]_groups members to be consistent to PIN_GROUP. Signed-off-by: Takashi Yoshii <takasi-y@ops.dti.ne.jp> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-12-10sh-pfc: r8a7790: Add Audio pin supportKuninori Morimoto1-0/+68
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-12-10sh-pfc: r8a7790: Add SSI pin supportKuninori Morimoto1-0/+239
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-12-10sh-pfc: Share common PORTCR macro definitionLaurent Pinchart5-45/+1
The macro is defined identically in four different locations. Share it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-10sh-pfc: Fix PINMUX_GPIO macroLaurent Pinchart1-1/+1
Commit 7cbb0e55e27e ("sh-pfc: Don't duplicate argument to PINMUX_GPIO macro") erronesouly modified the PINMUX_GPIO macro in a way that resulted in all pins being named "name". Fix the macro to name the pins correctly. Cc: stable@vger.kernel.org Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-03sh-pfc: sh7372: Fix pin bias setupLaurent Pinchart1-1/+1
When computing the pin configuration register offset the bias setup code erroneously compares the pin number range with the loop index instead of the pin number. Fix it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-03sh-pfc: r8a7740: Fix pin bias setupLaurent Pinchart1-1/+1
When computing the pin configuration register offset the bias setup code erroneously compares the pin number range with the loop index instead of the pin number. Fix it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-11-25sh-pfc: r8a7791: Fix DU pin groups organisationLaurent Pinchart1-9/+27
Rename the sync_1 group to sync as the device has a single sync pin group for the DU, move the cde_disp mux array right after the corresponding pins array, and split the clk_in pins in three separate groups as the pins can be used independently. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-10-27pinctrl: sh-pfc: r8a7791 PFC supportHisashi Nakamura5-0/+4230
Add PFC support for the r8a7791 SoC V2 including pin groups for on-chip devices such as MSIOF, SCIF, USB, MMC, SDHI, DU. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Kunihito Higashiyama <kunihito.higashiyama.ur@renesas.com> Signed-off-by: Yoshikazu Fujikawa <yoshikazu.fujikawa.ue@renesas.com> Signed-off-by: Nobuyuki HIRAI <nobuyuki.hirai.xe@renesas.com> Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com> [damm@opensource.se: Forward ported to upstream, minor fixes] Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-10-27sh-pfc: r8a7778: Add CAN pin groupsSergei Shtylyov1-0/+55
Add CAN data and clock pin groups to R8A7778 PFC driver. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-09-27sh-pfc: r8a7790: add pin definitions for the I2C3 interfaceGuennadi Liakhovetski1-0/+28
There are four I2C interfaces on r8a7790, each of them can be connected to one of the two respective I2C controllers, e.g. interface #0 can be configured to work with I2C0 or with IIC0. Additionally some of those interfaces can also use one of several pin sets. Interface #3 is special, because it can be used in automatic mode for DVFS. It only has one set of pins available and those pins cannot be used for anything else, they also lack the GPIO function. This patch uses the sh-pfc ability to configure pins, not associated with GPIOs and adds support for I2C3 to the r8a7790 PFC set up. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-09-24sh-pfc: r8a7790: Add I2C pin groups and functionsUlrich Hecht1-0/+82
Adds pinmux for i2c bus 1 and 2. (Pins for 0 and 3 are not multiplexed.) Signed-off-by: Ulrich Hecht <ulrich.hecht@gmail.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-09-24sh-pfc: r8a7778: Add SRU/SSI pin supportKuninori Morimoto1-0/+125
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-08-29Merge tag 'v3.11-rc7' into develLinus Walleij1-0/+1
Merged in this to avoid conflicts with the big locking fixes from upstream. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Conflicts: drivers/pinctrl/pinctrl-sunxi.c
2013-08-28pinctrl: sh-pfc: remove unnecessary platform_set_drvdata()Jingoo Han1-2/+0
The driver core clears the driver data to NULL after device_release or on probe failure. Thus, it is not needed to manually clear the device driver data to NULL. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-28pinctrl: Pass all configs to driver on pin_config_set()Sherman Yin1-18/+24
When setting pin configuration in the pinctrl framework, pin_config_set() or pin_config_group_set() is called in a loop to set one configuration at a time for the specified pin or group. This patch 1) removes the loop and 2) changes the API to pass the whole pin config array to the driver. It is now up to the driver to loop through the configs. This allows the driver to potentially combine configs and reduce the number of writes to pin config registers. All c files changed have been build-tested to verify the change compiles and that the corresponding .o is successfully generated. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <csd@broadcom.com> Reviewed-by: Matt Porter <matt.porter@linaro.org> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-14sh-pfc: r8a7790: Add DU pin groups and functionsLaurent Pinchart1-0/+134
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-14sh-pfc: r8a7790: Rename DU1_DOTCLKIN to DU_DOTCLKIN1Laurent Pinchart1-4/+4
Name the DU clock input 1 consistently with clock inputs 0 and 2. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-07-29Merge branch 'pinmux/next/fixes' of git://linuxtv.org/pinchartl/fbdev into develLinus Walleij6-629/+1093
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-07-29sh-pfc: r8a7790: Add VIN pin groups and functionsShinobu Uehara1-0/+106
Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-07-29sh-pfc: r8a7790: Add USB pin groups and functionsShinobu Uehara1-0/+42
Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com> Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-07-29sh-pfc: r8a7790: Add SCIF2 pin groups and functionsLaurent Pinchart1-0/+32
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-07-29sh-pfc: r8a7790: Add MSIOF pin groups and functionsKunihito Higashiyama1-0/+236
Signed-off-by: Kunihito Higashiyama <kunihito.higashiyama.ur@renesas.com> Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-07-29sh-pfc: r8a7790: Sort pin groups and functions alphabeticallyLaurent Pinchart1-265/+265
Navigating through the source code is hard enough without having to manually search for groups and functions. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-07-29sh-pfc: r8a7790: Fix miscellaneous pinmux configuration tables mistakesShinya Kuribayashi1-16/+15
Fix erroneous entries in the pinmux configuration tables that affect HSCIF, I2C, LBSC, SCIF, SSI and VIN operation. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-07-29sh-pfc: r8a7790: Add SCIF2 pins configuration supportShinya Kuribayashi1-17/+23
Update the pinmux configuration tables to support the SCIF2 pins (TX2/TX2_B, RX2/RX2_B, SCK2). Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-07-29sh-pfc: r8a7790: Add TCLK1 pin configuration supportShinya Kuribayashi1-3/+4
Update the pinmux configuration tables to support the TCLK1 pin. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-07-29sh-pfc: r8a7790: Swap SCIFA2_RXD_B and HRX0_C configurationsShinya Kuribayashi1-8/+8
The SCIFA2 RXD_B and HRX0_C pins have their pinmux configuration data swapped, fix it. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2013-07-29sh-pfc: r8a7790: Remove deprecated SPV_EVEN pinShinya Kuribayashi1-4/+3
The pins have been removed from the datasheet, remove them here as well. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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