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2020-09-15pinctrl: Rename sh-pfc to renesasGeert Uytterhoeven1-6492/+0
The drivers/pinctrl/sh-pfc subdirectory was originally created to group pin control drivers for various Renesas SuperH and SH-Mobile platforms. However, the name "sh-pfc" no longer reflects its contents, as the directory now contains pin control drivers for Renesas SuperH, ARM32, and ARM64 SoCs. Hence rename the subdirectory from drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas, and the related Kconfig symbol from PINCTRL_SH_PFC to PINCTRL_RENESAS. Rename the git branch in MAINTAINERS, too, for consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200909131534.12897-3-geert+renesas@glider.be
2019-12-20pinctrl: sh-pfc: r8a77965: Fix DU_DOTCLKIN3 drive/bias controlGeert Uytterhoeven1-3/+3
R-Car Gen3 Hardware Manual Errata for Rev. 2.00 of October 24, 2019 changed the configuration bits for drive and bias control for the DU_DOTCLKIN3 pin on R-Car M3-N, to match the same pin on R-Car H3. Update the driver to reflect this. After this, the handling of drive and bias control for the various DU_DOTCLKINx pins is consistent across all of the R-Car H3, M3-W, M3-W+, and M3-N SoCs. Fixes: 86c045c2e4201e94 ("pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191113101653.28428-1-geert+renesas@glider.be
2019-10-14pinctrl: sh-pfc: pfc-r8a77965: Fix typo in pinmux macro for SCL3Keiya Nobuta1-1/+1
SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro. Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com> Link: https://lore.kernel.org/r/20191008060619.30237-4-nobuta.keiya@fujitsu.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-01pinctrl: sh-pfc: r8a77965: Add R8A774B1 PFC supportBiju Das1-409/+452
Renesas RZ/G2N (r8a774b1) is pin compatible with R-Car M3-N (r8a77965), however it doesn't have several automotive specific peripherals. Add a r8a77965 specific pin groups/functions along with common pin groups/functions for supporting both r8a77965 and r8a774b1 SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1568881036-4404-9-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-06-04pinctrl: sh-pfc: r8a77965: Use new macros for non-GPIO pinsGeert Uytterhoeven1-156/+151
Update the R-Car M3-N pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car M3-N SiP (in 39x39 BGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-05-21pinctrl: sh-pfc: r8a77965: Add TPU pins, groups and functionsGeert Uytterhoeven1-0/+42
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs on the R-Car M3-N SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21pinctrl: sh-pfc: Move PIN_NONE to shared header fileGeert Uytterhoeven1-28/+27
Several drivers have identical definitions for PIN_NONE. Provide a definition with a SH_PFC_ prefix for general use in sh_pfc.h, and convert all drivers over to use it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21pinctrl: sh-pfc: Add SH_PFC_PIN_CFG_PULL_UP_DOWN shorthandGeert Uytterhoeven1-7/+5
It is very common for a pin to support both pull-up and pull-down functionality. Hence add a shorthand SH_PFC_PIN_CFG_PULL_UP_DOWN. This not only reduces typing, but also avoids the need for several line breaks, and makes many overly long lines shorter, improving readability. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21pinctrl: sh-pfc: Rename 2-parameter CPU_ALL_PORT() variantGeert Uytterhoeven1-1/+1
There are two variants of the CPU_ALL_PORT() macro in use: 1. A three-parameter variant, to be provided for SoCs with a linear GPIO pin space ("PORT style"), 2. A two-parameter variant, to be provided for SoCs with 32-port GPIO banks ("GP port style"). Rename the 2-parameter variant to CPU_ALL_GP(), to avoid confusion, and to increase naming consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-04pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functionsTakeshi Kihara1-24/+87
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC. These pins are physically muxed with other pins. Therefore, setup of MOD_SEL is needed for exclusive control with other pins. [takeshi.kihara.df: add blank lines after function declarations] Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [uli: use standard macros PINMUX_IPSR_PHYS and PINMUX_IPSR_PHYS_MSEL] Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDFTakeshi Kihara1-11/+11
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50 of Feb 12, 2019, the sel_ndfc MOD_SEL register bit is renamed to sel_ndf. Update the pin control drivers to reflect this. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Update R-Car E3] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}Takeshi Kihara1-11/+11
According to the R-Car Gen3 Hardware Manual Errata for Rev 0.80 of Dec 22, 2017, and the Errata for Rev 1.50 of Dec 25, 2018, MOD_SEL0 register bits 3, 4, 17, and 18 are renamed from SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}. Update the pin control drivers to reflect this. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pinTakeshi Kihara1-2/+1
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Jun 4, 2018, the CC5_OSCOUT pin is removed. Update the pin control drivers to reflect this. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Update R-Car V3M, V3H] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functionsTakeshi Kihara1-4/+4
The HDMI CEC function is not supported by the R-Car Gen3 Hardware Manual Rev 1.00. Therefore, delete the corresponding pin groups and functions, and rename the HDMI[01]_CEC definitions to match their GPIO functionality. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Squashed several commits] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macroGeert Uytterhoeven1-9/+12
Currently the PINMUX_CFG_REG_VAR() macro must be followed by initialization data, specifying all enum IDs. Hence the macro itself does not know anything about the enum IDs, preventing the macro from performing any validation on it. Make the macro accept the enum IDs as a parameter, and update all users. Note that array data enclosed by curly braces cannot be passed to a macro as a parameter, hence both the register field widths and the enum IDs are wrapped using the GROUP() macro. No functional changes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macroGeert Uytterhoeven1-54/+54
Currently the PINMUX_CFG_REG() macro must be followed by initialization data, specifying all enum IDs. Hence the macro itself does not know anything about the enum IDs, preventing the macro from performing any validation on it. Make the macro accept the enum IDs as a parameter, and update all users. Note that array data enclosed by curly braces cannot be passed to a macro as a parameter, hence the enum IDs are wrapped using a new macro GROUPS(). No functional changes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02pinctrl: sh-pfc: Add missing #include <linux/errno.h>Geert Uytterhoeven1-0/+1
Source files using -Exxx error codes should include <linux/errno.h>. On ARM, this header file is included indirectly; on SuperH, it is not, leading to "error: ‘EINVAL’ undeclared" failures when enabling compile-testing later. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-18pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resumeMarek Vasut1-0/+2
The TDSELCTRL register is responsible for configuring the SDHI/MMC clock return path delay and may be adjusted by the bootloader. Retain the value across suspend/resume to prevent hardware instability after resume. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-02-11pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functionsTakeshi Kihara1-0/+350
This patch adds DRIF{0,1,2,3} pins, groups and functions to the R8A77965 SoC. Based on a similar patch of the R8A7796 PFC driver by Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-02-11pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functionsTakeshi Kihara1-0/+48
This patch adds TMU TCLK{1,2} pins, groups and functions to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-01-21pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3Geert Uytterhoeven1-3/+3
Unlike R-Car M3-W, R-Car M3-N does not have DU_DOTCLKIN2, but the corresponding pin carries the DU_DOTCLKIN3 signal. Correct all references to DU_DOTCLKIN2 to fix this. This change does not have any runtime effect, as it only changes an internal enum name, and a comment. Fixes: 490e687eb8b274b5 ("pinctrl: sh-pfc: Initial R-Car M3-N support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-19pinctrl: sh-pfc: r8a77965: Add CAN FD pins, groups and functionsTakeshi Kihara1-0/+42
This patch adds CAN FD{0,1} pins, groups and functions to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19pinctrl: sh-pfc: r8a77965: Add CAN pins, groups and functionsTakeshi Kihara1-0/+58
This patch adds CAN{0,1} pins, groups and functions to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13pinctrl: sh-pfc: r8a77965: Add VIN[4|5] groups/functionsJacopo Mondi1-0/+270
The VIN4 and VIN5 interfaces support parallel video input. Add pin, mux and functions definitions for VIN4 and VIN5 for R-Car M3-N. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-08-28pinctrl: sh-pfc: r8a77965: Add Audio SSI pin supportHoan Nguyen An1-0/+232
Add Audio SSI pin support for r8a77965. Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-08-28pinctrl: sh-pfc: r8a77965: Add Audio clock pin supportHoan Nguyen An1-0/+160
Add Audio clock pin support for r8a77965. Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-08-27pinctrl: sh-pfc: r8a77965: Add SATA pins, groups and functionsTakeshi Kihara1-0/+27
This patch adds SATA0 pin, group and function to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [wsa: rebased to upstream base] Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-07-16pinctrl: sh-pfc: r8a77965: Add HSCIF pins, groups, and functionsTakeshi Kihara1-0/+333
This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-05-23pinctrl: sh-pfc: rcar-gen3: Fix grammar in static pin commentsGeert Uytterhoeven1-3/+3
The comment block explaining the rationale for static pins contains grammar errors. It appeared first in the pin control driver for R-Car H3 ES1.x, and spread to R-Car M3-W, H3 ES2.0, and M3-N later. Fix the grammar in all copies at once. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2018-05-23pinctrl: sh-pfc: r8a77965: Add I2C pin supportNiklas Söderlund1-0/+77
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-05-16pinctrl: sh-pfc: r8a77965: Add SDHI pins, groups and functionsTakeshi Kihara1-0/+326
This patch adds SDHI{0,1,2,3} pins, groups and functions to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Tested-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-05-16pinctrl: sh-pfc: r8a77965: Add DU RGB output pins, groups and functionsKieran Bingham1-0/+116
This patch adds pins, groups and functions for parallel RGB output signals from DU. The HDMI and TCON pins are added to separate groups. Based on a similar patch of the R8A7796 PFC driver by Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [Kieran: Rebase on top of tree] Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-05-16pinctrl: sh-pfc: r8a77965: Fixup incorrect SPDX identifierThomas Gleixner1-1/+1
GPL-2. is not a valid SPDX identifier. Make it GPL-2.0 Fixes: 490e687eb8b2 ("pinctrl: sh-pfc: Initial R-Car M3-N support") Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Jacopo Mondi <jacopo+renesas@jmondi.org> Cc: Rob Herring <robh@kernel.org> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-05-16pinctrl: sh-pfc: r8a77965: Add PWM pins, groups and functionsTakeshi Kihara1-0/+153
This patch adds PWM{0,1,2,3,4,5,6} pins, groups and functions to R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-05-16pinctrl: sh-pfc: r8a77965: Add MSIOF pins, groups and functionsTakeshi Kihara1-0/+912
This patch adds MSIOF{0,1,2,3} pins, groups and functions to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Correct MSIOF3 SS2_E comment] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-03-21pinctrl: sh-pfc: r8a77965: Rename EtherAVB "mdc" pin group to "mdio"Geert Uytterhoeven1-4/+6
On other Renesas SoCs, the pin group for the MDIO bus is named "mdio" instead of "mdc". Fix the inconsistency, while retaining backwards compatibility with old DTBs using a pin group alias. Fixes: fa3e8b71b955af86 ("pinctrl: sh-pfc: r8a77965: Add EtherAVB groups/functions") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2018-03-05pinctrl: sh-pfc: r8a77965: Add USB3.0 host pins, groups and functionsTakeshi Kihara1-0/+16
This patch adds USB30 (USB3.0 host) pin, group and function to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-05pinctrl: sh-pfc: r8a77965: Add USB2.0 host pins, groups and functionsTakeshi Kihara1-0/+32
This patch adds USB{0,1} (USB2.0 host) pins, groups and functions to the R8A77965 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-28pinctrl: sh-pfc: r8a77965: Add support for INTC-EX IRQ pinsTakeshi Kihara1-0/+61
Most pins on the R8A77965 SoC can be configured in GPIO mode for interrupt and GPIO functionality, while a couple of them can also be routed to the INTC-EX hardware block (formerly known as IRQC). On R8A77965 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and this patch adds support for them to the PFC driver as "intc_ex_irqN". Based on a similar patch for the R8A7795 PFC driver by Magnus Damm <damm+renesas@opensource.se>. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20pinctrl: sh-pfc: r8a77965: Add EtherAVB groups/functionsJacopo Mondi1-0/+110
Add EtherAVB groups and functions definitions for R-Car M3-N. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20pinctrl: sh-pfc: r8a77965: Add SCIFs groups/functionsJacopo Mondi1-0/+296
Add SCIF[0-5] groups and pin function definitions for R-Car M3-N. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-20pinctrl: sh-pfc: Initial R-Car M3-N supportJacopo Mondi1-0/+2726
Add initial PFC support for R-Car M3-N (r8a77965) SoC. No groups or functions defined, just pin and registers enumeration. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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