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path: root/drivers/pinctrl/pinctrl-tegra.h
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2014-04-22pinctrl: tegra: add missing kerneldocStephen Warren1-0/+4
The kerneldoc for struct tegra_pingroup didn't describe all of the fields in the struct. Add some extra kerneldoc to fix that. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: tegra: reduce size of data table fieldsStephen Warren1-2/+2
The range of npins and function ID values is small enough to fit into a u8. Use this type rather than unsigned to shrink the pinmux data tables. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: tegra: remove fsafe from data tablesStephen Warren1-1/+0
The fsafe value in the pingroup data tables is only used to implement tegra_pinctrl_disable(). The only reason this function is called is when dynamically switching between pinmux states, i.e. when disabling the old state before programming the new state. It's simpler to have the new target state define the expected value of each pin (and all current DTs do that). This also gives more flexibility, since it allows individual boards explicit control over the "inactive" mux function for each pin, rather than requiring it to be an SoC-specific value. Assuming this, we can get rid of the fsafe value from the driver completely, thus saving some more space in the driver tables. While re-writing the content of tegra124_pingroups[], fix the indentation to use a TAB instead of spaces. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: tegra: remove redundant data table fieldsStephen Warren1-71/+53
Any SoC which supports the einput, odrain, lock, ioreset, or rcv_sel options has the relevant HW register fields in the same register as the mux function selection. Similarly, the drvtype option is always in the drive register, if it is supported at all. Hence, we don't need to have struct *_reg fields in the pin group table to define which register and bank to use for those options. Delete this to save space in the driver's data tables. However, many of those options are not supported on all SoCs, or not supported on some pingroups. We need a way to detect when they are supported. Previously, this was indicated by setting the struct *_reg field to -1. With the struct *_reg fields removed, we use the struct *_bit fields for this purpose instead. The struct *_bit fields need to be expanded from 5 to 6 bits in order to store a value outside the valid HW bit range of 0..31. Even without removing the struct *_reg fields, we still need to add code to validate the struct *_bit fields, since some struct *_bit fields were already being set to -1, without an option-specific struct *_reg field to "guard" them. In other words, before this change, the pinmux driver might allow some unsupported options to be written to HW. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12pinctrl: tegra: dynamically calculate function list of groupsStephen Warren1-2/+2
The per-SoC data structures for Tegra pinctrl stored some information in a redundant way. Specifically, the list of groups that each function could be muxed onto was stored once explicitly, and also as part of the definition of each group. Eliminate this redundancy, and calculate each function's list of valid groups at pinctrl probe time. This removes thousands of lines of code from the pinctrl driver and ~16K from the vmlinux binary size, and adds only about 500uS to the boot process (on Tegra30; newer SoCs will likely be faster still). Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-18pinctrl: tegra: add support for rcv-sel and drive typePritesh Raithatha1-0/+16
NVIDIA's Tegra114 added two more configuration parameter in pinmux i.e. rcv-sel and drive type. rcv-sel: Select between High and Normal VIL/VIH receivers. RCVR_SEL=1: High VIL/VIH RCVR_SEL=0: Normal VIL/VIH drv_type: Ouptput drive type: 33-50 ohm driver: 0x1 66-100ohm driver: 0x0 Add support of these parameters to be configure from DTS file. Tegra20 and Tegra30 does not support this configuration and hence initialize their pinmux structure with reg = -1. Originally written by Pritesh Raithatha. Changes by ldewangan: - remove drvtype_width as it is always 2. - Better describe the change. Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-09-14pinctrl: tegra: move pinconf-tegra.h content into drivers/pinctrlStephen Warren1-0/+44
Now that Tegra's pinmux is configured solely from device tree, there's no need for the pinconf types to be defined in arch/arm/mach-tegra/. Move it into the pinctrl directory to clean up mach-tegra, as a pre- requisite for single-zImage. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2012-04-18pinctrl: tegra: refactor probe handlingStephen Warren1-20/+3
Rather than having a single tegra-pinctrl driver that determines whether it's running on Tegra20 or Tegra30, instead have separate drivers for each that call into utility functions to implement the majority of the driver. This change is based on review feedback of the SPEAr pinctrl driver, which had originally copied to Tegra driver structure. This requires that the two drivers have unique names. Update a couple spots in arch/arm/mach-tegra for the name change. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2012-03-06pinctrl: add a driver for NVIDIA TegraStephen Warren1-0/+163
This adds a driver for the Tegra pinmux, and required parameterization data for Tegra20 and Tegra30. The driver is initially added with driver name and device tree compatible value that won't cause this driver to be used. A later change will switch the pinctrl driver to use the correct values, switch the old pinmux driver to be disabled, and update all code that uses the old pinmux APIs to use the new pinctrl APIs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net> [squashed "fix case of Tegra30's foo_groups[] arrays"] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>