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2014-01-21Merge tag 'pinctrl-v3.14-1' of ↵Linus Torvalds1-6/+7
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull bulk pin control changes from Linus Walleij: "This has been queued and tested for a while. Lots of action here, like in the GPIO tree, embedded stuff like this is really hot now it seems. Details in the signed tag. I'm especially happy about the Qualcomm driver as it is used in such a huge subset of mobile handsets out there, and these platforms in general need better upstream support - New driver for the Qualcomm TLMM pin controller and its msm8x74 subdriver. - New driver for the Broadcom Capri BCM281xx SoC. - New subdriver for the imx25 pin controller. - New subdriver for the Tegra124 pin controller. - Lock GPIO lines as IRQs for select combined pin control and GPIO drivers for baytrail and sirf. - Some semi-big refactorings and extenstions to the sirf driver. - Lots of patching, cleanup and fixing in the Renesas "PFC" driver and associated subdrivers as usual. It is settling down a little bit now it seems. - Minor fixes and incremental updates here and there as usual" * tag 'pinctrl-v3.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits) pinctrl: sunxi: Honor GPIO output initial vaules pinctrl: capri: add dependency on OF ARM: bcm11351: Enable pinctrl for Broadcom Capri SoCs ARM: pinctrl: Add Broadcom Capri pinctrl driver pinctrl: Add pinctrl binding for Broadcom Capri SoCs pinctrl: Add void * to pinctrl_pin_desc pinctrl: st: Fix a typo in probe pinctrl: Fix some typos and grammar issues in the documentation pinctrl: sirf: lock IRQs when starting them pinctrl: sirf: put gpio interrupt pin into input status automatically pinctrl: sirf: use only one irq_domain for the whole device node pinctrl: single: fix infinite loop caused by bad mask pinctrl: single: fix pcs_disable with bits_per_mux pinctrl: single: fix DT bindings documentation pinctrl: as3722: Set pin to output mode for some function pinctrl: sirf: add pin group for USP0 with only RX or TX frame sync pinctrl: sirf: fix the pins of sdmmc5 connected with TriG pinctrl: sirf: add lost usp1_uart_nostreamctrl group for atlas6 pinctrl: sunxi: Add Allwinner A20 clock output pin functions pinctrl/lantiq: fix typo ...
2014-01-20pinctrl: sunxi: Honor GPIO output initial vaulesChen-Yu Tsai1-6/+7
Some GPIO users, such as fixed-regulator, request GPIO output with initial value of 1. This was ignored by sunxi driver. Cc: stable@vger.kernel.org Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-12-04gpio/pinctrl: make gpio_chip members typed booleanLinus Walleij1-1/+1
This switches the two members of struct gpio_chip that were defined as unsigned foo:1 to bool, because that is indeed what they are. Switch all users in the gpio and pinctrl subsystems to assign these values with true/false instead of 0/1. The users outside these subsystems will survive since true/false is 1/0, atleast we set some kind of more strict typing example. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-30pinctrl: sunxi: Fix off-by-one for valid offset range checkingAxel Lin1-1/+1
The valid offset range should be 0 ... chip->ngpio - 1. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-30pinctrl: sunxi: drop lock on error pathLinus Walleij1-1/+3
I forgot to drop the lock for the return inside the loop protected by the spinlock in the pin config routine when merging in -rc7 in commit 6ad30ce046aefbdc3848232c665a728860d7bb68 Reported-by: Sherman Yin <syin@broadcom.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-29Merge tag 'v3.11-rc7' into develLinus Walleij1-5/+53
Merged in this to avoid conflicts with the big locking fixes from upstream. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Conflicts: drivers/pinctrl/pinctrl-sunxi.c
2013-08-28pinctrl: Pass all configs to driver on pin_config_set()Sherman Yin1-36/+41
When setting pin configuration in the pinctrl framework, pin_config_set() or pin_config_group_set() is called in a loop to set one configuration at a time for the specified pin or group. This patch 1) removes the loop and 2) changes the API to pass the whole pin config array to the driver. It is now up to the driver to loop through the configs. This allows the driver to potentially combine configs and reduce the number of writes to pin config registers. All c files changed have been build-tested to verify the change compiles and that the corresponding .o is successfully generated. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <csd@broadcom.com> Reviewed-by: Matt Porter <matt.porter@linaro.org> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-23pinctrl: sunxi: Add Allwinner A20 pins setMaxime Ripard1-0/+1
The Allwinner A20 is pin-compatible with the older A10, so the two pin set are quite similar. However, since the A20 has new features, we can't just use the A10 pin set as is, and we need to define our own for the A20. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-23pinctrl: sunxi: Add Allwinner A31 pins setMaxime Ripard1-0/+1
The Allwinner A31 SoC uses the same IP than the one found in the A10/A13, with only different pins. Add the pins and the associated functions found in the A31. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-07pinctrl: sunxi: Fix incorrect NULL checkSachin Kamat1-1/+1
*map should be tested for NULL instead of map as kmalloc pointer is assigned to it. This also fixes a potential null pointer dereference bug later in the code. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-08-07pinctrl: sunxi: Add spinlocksMaxime Ripard1-3/+52
The current code use no locking at all, which is obviously not that great and can lead to concurrency issues, especially with the newer SMP SoCs from Allwinner. Add some locking where it's needed. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
2013-08-07pinctrl: sunxi: Fix gpio_set behaviourMaxime Ripard1-1/+7
The current gpio_set function is ignoring the previous value set in the GPIO value register, which leads in erasing the values already set for the other GPIOs in the same bank when setting the value of a given GPIO. Add the usual read/mask/write pattern to fix this brown paper bag bug. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
2013-08-07pinctrl: sunxi: Read register before writing to it in irq_set_typeMaxime Ripard1-1/+4
The current irq_set_type code doesn't read the current register value before writing to it, leading to the older programmed values being overwritten and everything but the latest value being reset. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
2013-06-17pinctrl: sunxi: Add Allwinner A10s pinsMaxime Ripard1-0/+1
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-17pinctrl: sunxi: Move the pins definitions to a separate headerMaxime Ripard1-1360/+1
It will allow us to have a cleaner separation between the data needed by the driver to work, and the core logic of the driver in itself, and will allow having too much noise in the core driver in the future. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-16pinctrl: sunxi: Add external interrupt functionsMaxime Ripard1-26/+73
The A10 and A13 has a few pins that can be muxed into a particular function that can be used as an interrupt source. Add the available pins for such functions to the A10 and A13 description array. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-16pinctrl: sunxi: Add external interrupts supportMaxime Ripard1-0/+155
The port controller IP found in the Allwinner A10 and A13 can use few of the pins it manage as an interrupt source, called external interrupts in the datasheet. The number of these external interrupts are SoCs specific, but the current upper limit is 32. In order to work, the external interrupts' pins have to be muxed to a specific function to generate an interrupt. This patch adds the irqchip and the needed logic to use the PIO controller as an interrupt controller. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-06-16pinctrl: sunxi: Search the description array by pin idMaxime Ripard1-21/+29
Avoid to use expensive string manipulation functions and search by pin id when possible. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-05-27pinctrl: sunxi: fix error return code in sunxi_pinctrl_probe()Wei Yongjun1-1/+3
Fix to return a negative error code from the devm_clk_get() error handling case instead of 0, as done elsewhere in this function. Introduced by commit 950707c0eb5c7aeaa2c446a04c824f4be686d2f6 (pinctrl: sunxi: add clock support) Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-05-27pinctrl: Don't override the error code in probe error handlingAxel Lin1-1/+2
Otherwise, we return 0 in probe error paths when gpiochip_remove() returns 0. Also show error message if gpiochip_remove() fails. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Tony Prisk <linux@prisktech.co.nz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-09pinctrl: sunxi: Rename wemac functions to emacMaxime Ripard1-18/+18
The pin functions associated to the ethernet controller were introduced with the label "wemac", which was the name of the ethernet driver in the allwinner source tree, while the real name of the IP is actually "emac", as advertised in several documents including the datasheet. Since this is part of the device tree bindings, and that these part of the bindings have not yet be released in a kernel version, it seems like the good timing to change it and assure consistency. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-04-03pinctrl: sunxi: add clock supportEmilio López1-0/+8
For the port controller to work, we need to enable the apb0_pio gate. This commit adds the ability to enable one clock specified on the device tree to the pinctrl driver. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-07pinctrl: sunxi: Add Allwinner A13 pin functionsMaxime Ripard1-70/+169
The initial driver contained only a limited set of pins functions because we lacked of documentation on it. Now that we have such documentation, finish to fill the array. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-07pinctrl: sunxi: Add Allwinner A10 pin functionsMaxime Ripard1-162/+571
The initial driver contained only a limited set of pins functions because we lacked of documentation on it. Now that we have such documentation, finish to fill the array. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-03-07pinctrl: Declare operation structures as constLaurent Pinchart1-3/+3
The pinconf, pinctrl and pinmux operation structures hold function pointers that are never modified. Declare them as const. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-02-05pinctrl: sunxi: add of_xlate functionMaxime Ripard1-0/+20
Since the pin controller of sunxi chips is represented as a single bank in the driver. Since this is neither convenient nor represented that way in the datasheets, define a custom of_xlate function with the layout <bank pin flag> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-02-01ARM: pinctrl: sunxi: Add the pinctrl pin set for Allwinner A10Maxime Ripard1-0/+554
Since the Allwinner SoCs variants don't have the same set of pins to handle, we need to declare the pin ranges available. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-02-01pinctrl: sunxi: Document sun5i pins functionsMaxime Ripard1-4/+4
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-29ARM: sunxi: gpio: Add Allwinner SoCs GPIO driversMaxime Ripard1-2/+132
The IP responsible for the muxing on the Allwinner SoCs are also handling the GPIOs on the system. This patch adds the needed driver that relies on the pinctrl driver for most of its operations. The number of pins available for GPIOs operations are already declared in the pinctrl driver, we only need to probe a generic driver to handle the banks available for each SoC. This driver has been tested on a A13-Olinuxino. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-22ARM: pinctrl: sunxi: Add the pinctrl pin set for sun5iMaxime Ripard1-0/+253
Since the Allwinner SoCs variants don't have the same set of pins to handle, we need to declare the pin ranges available. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-22ARM: sunxi: Add pinctrl driver for Allwinner SoCsMaxime Ripard1-0/+548
The Allwinner SoCs have an IP module that handle both the muxing and the GPIOs. This IP has 8 banks of 32 bits, with a number of pins actually useful for each of these banks varying from one to another, and depending on the SoC used on the board. This driver only implements the pinctrl part, the gpio part will come eventually. Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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