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path: root/drivers/pinctrl/intel/pinctrl-cannonlake.c
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2020-09-30pinctrl: cannonlake: Modify COMMUNITY macros to be consistentAndy Shevchenko1-11/+11
Modify COMMUNITY macros to be consistent with Tiger Lake and others. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20200929110306.40852-2-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-04-14pinctrl: cannonlake: Use generic flag for special GPIO base treatmentAndy Shevchenko1-30/+28
Since we have a generic flag for special GPIO base treatment, use it in the driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-08-07pinctrl: cannonlake: Provide Interrupt Status register offsetAndy Shevchenko1-0/+2
Since some of the GPIO controllers use different Interrupt Status offset, it make sense to provide it explicitly in the driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-11-08pinctrl: cannonlake: Code formatting fixesAndy Shevchenko1-1/+1
Remove comma from terminator line to allow compiler fail in case an entry has been put in a wrong place by any weird reason. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-11-08pinctrl: cannonlake: Get rid of unneeded ->probe() stubAndy Shevchenko1-6/+1
The local ->probe() stub does nothing except calling a generic Intel pin control probe function. Thus, it's not needed and generic function may be called directly. Convert the driver accordingly. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2018-10-01Merge tag 'v4.19-rc6' into develLinus Walleij1-14/+21
This is the 4.19-rc6 release I needed to merge this in because of extensive conflicts in the MSM and Intel pin control drivers. I know how to resolve them, so let's do it like this. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-25pinctrl: cannonlake: Fix HOSTSW_OWN register offset of H variantMika Westerberg1-13/+20
It turns out the HOSTSW_OWN register offset is different between LP and H variants. The latter should use 0xc0 instead so fix that. Link: https://bugzilla.kernel.org/show_bug.cgi?id=199911 Fixes: a663ccf0fea1 ("pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support") Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18pinctrl: intel: Move linux/pm.h to the local headerAndy Shevchenko1-1/+0
We now using a common macro for PM operations in pin control drivers for Intel SoCs, and since that macro relies on the definition and macro from linux/pm.h header file, it's logical to include it directly in pinctrl-intel.h. Otherwise it's a bit fragile and requires a proper ordering of header inclusion in C files. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-18pinctrl: cannonlake: Fix gpio base for GPP-ESimon Detheridge1-1/+1
The gpio base for GPP-E was set incorrectly to 258 instead of 256, preventing the touchpad working on my Tong Fang GK5CN5Z laptop. Buglink: https://bugzilla.kernel.org/show_bug.cgi?id=200787 Signed-off-by: Simon Detheridge <s@sd.ai> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-31pinctrl: cannonlake: Define PM ops via INTEL_PINCTRL_PM_OPS()Andy Shevchenko1-4/+1
Instead of open coding same structure definition for PM operations, replace it with a common macro. No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-08-31pinctrl: cannonlake: Convert to use intel_pinctrl_probe_by_hid()Andy Shevchenko1-10/+3
Get rid of code duplication by converting to use intel_pinctrl_probe_by_hid(). No functional change intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-30pinctrl: cannonlake: Fix community ordering for H variantAndy Shevchenko1-6/+2
The driver was written based on an assumption that BIOS provides unordered communities in ACPI DSDT. Nevertheless, it seems that BIOS getting fixed before being provisioned to OxM:s. So does driver. BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=199911 Reported-by: Marc Landolt <2009@marclandolt.ch> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Fixes: a663ccf0fea1 ("pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support") Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-07-02pinctrl: intel: Convert to use SPDX identifierAndy Shevchenko1-4/+1
Reduce size of duplicated comments by switching to use SPDX identifier. No functional change. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-29pinctrl: cannonlake: Align GPIO number space with WindowsMika Westerberg1-31/+34
The Cannon Lake Windows GPIO driver always exposes 32 pins per "bank" regardless of whether the hardware actually has that many pins in a pad group. This means that there are gaps in the GPIO number space even if such gaps do not exist in the real hardware. To make things worse the BIOS is also using the same scheme, so for example on Cannon Lake-LP vGPIO 39 (vSD3_CD_B) the ACPI GpioInt resource has number 231 instead of the expected 180 (which would be the hardware number). To make SD card detection and other GPIOs working properly in Linux we align the pinctrl-cannonlake GPIO numbering to follow the Windows GPIO driver numbering taking advantage of the gpio_base field introduced in the previous patch. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-22pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller supportMika Westerberg1-1/+423
This is desktop version Intel Cannon Lake PCH. The GPIO hardware is the same but pin list differs a bit. Add support for this to the existing Cannon Lake pin controller driver. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-06-09pinctrl: intel: Add Intel Cannon Lake PCH pin controller supportMika Westerberg1-0/+442
This adds pinctrl/GPIO support for Intel Cannon Lake PCH. The Cannon Lake PCH GPIO is based on newer version of the Intel GPIO hardware. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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