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2020-05-18phy: omap-usb2: Clean up exported headerRoger Quadros1-4/+56
Move private definitions from header to phy-omap-usb2.c file. Get rid of unused data structures usb_dpll_params and omap_usb_phy_type. Signed-off-by: Roger Quadros <rogerq@ti.com> Link: https://lore.kernel.org/r/20200515080518.26870-2-rogerq@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-18phy: phy-bcm-ns2-usbdrd: Constify phy_opsRikard Falkeborn1-1/+1
phy_ops are never modified and can therefore be made const to allow the compiler to put it in read-only memory. Before: text data bss dec hex filename 7831 3144 128 11103 2b5f drivers/phy/broadcom/phy-bcm-ns2-usbdrd.o After: text data bss dec hex filename 7959 3016 128 11103 2b5f drivers/phy/broadcom/phy-bcm-ns2-usbdrd.o Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200516120441.7627-2-rikard.falkeborn@gmail.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-18phy: phy-brcm-usb: Constify static structsRikard Falkeborn1-8/+8
A number of structs were not modified and can therefore be made const to allow the compiler to put them in read-only memory. In order to do so, update a few functions that don't modify there input to take pointers to const. Before: text data bss dec hex filename 15511 6448 64 22023 5607 drivers/phy/broadcom/phy-brcm-usb.o After: text data bss dec hex filename 16058 5936 64 22058 562a drivers/phy/broadcom/phy-brcm-usb.o Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200516120441.7627-4-rikard.falkeborn@gmail.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-18phy: sr-usb: Constify phy_opsRikard Falkeborn1-1/+1
phy_ops are never modified and can therefore be made const to allow the compiler to put it in read-only memory. Before: text data bss dec hex filename 4310 1244 0 5554 15b2 drivers/phy/broadcom/phy-bcm-sr-usb.o After: text data bss dec hex filename 4438 1116 0 5554 15b2 drivers/phy/broadcom/phy-bcm-sr-usb.o Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200516120441.7627-3-rikard.falkeborn@gmail.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-15phy: phy-cadence-salvo: add phy .init APIPeter Chen1-1/+11
The .init is used for one-time PHY's initialization, and .power_on is called many times during the device lifecycle. Signed-off-by: Peter Chen <peter.chen@nxp.com> Link: https://lore.kernel.org/r/20200513125605.5545-1-peter.chen@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-15phy: amlogic: meson8b-usb2: Add a compatible string for Meson8m2Martin Blumenstingl2-2/+6
The 3.10 vendor kernel sets the ACA_ENABLE bit on Meson8b, Meson8m2 and GXBB, but not on Meson8. Add a compatible string for Meson8m2 which also sets that bit. While here, also update the Kconfig text and MODULE_DESCRIPTION. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Thomas Graichen <thomas.graichen@gmail.com> Link: https://lore.kernel.org/r/20200512222424.549351-7-martin.blumenstingl@googlemail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-15phy: amlogic: meson8b-usb2: unset the IDDQ bit during PHY power-onMartin Blumenstingl1-12/+32
The vendor driver unsets the set_iddig bit during power-on as well and sets it when suspending the PHY. I did not notice this in the vendor driver first, because it's part of the dwc_otg driver there (instead of their PHY code). While here, also add all other REG_DBG_UART register bit definitions. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Thomas Graichen <thomas.graichen@gmail.com> Link: https://lore.kernel.org/r/20200512222424.549351-6-martin.blumenstingl@googlemail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-15phy: amlogic: meson8b-usb2: Don't set REG_ADP_BC_ACA_ENABLE on Meson8Martin Blumenstingl1-10/+38
Skip setting REG_ADP_BC_ACA_ENABLE on Meson8 SoCs and polling for the REG_ADP_BC_ACA_PIN_FLOAT bit. The vendor also skips this part on Meson8 SoCs. This fixes initialization of the host-only USB PHY on Meson8 which would otherwise fail with "USB ID detect failed!". Fixes: 4a3449d1a0a10c ("phy: meson8b-usb2: add support for the USB PHY on Meson8 SoCs") Reported-by: Thomas Graichen <thomas.graichen@gmail.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Thomas Graichen <thomas.graichen@gmail.com> Link: https://lore.kernel.org/r/20200512222424.549351-5-martin.blumenstingl@googlemail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-15phy: amlogic: meson8b-usb2: Use a MMIO regmapMartin Blumenstingl2-39/+35
Using a MMIO regmap and switch to regmap_update_bits() to simplify the code in the driver. Also switch to devm_platform_ioremap_resource() instead of open-coding it. No functional changes intended. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Thomas Graichen <thomas.graichen@gmail.com> Link: https://lore.kernel.org/r/20200512222424.549351-4-martin.blumenstingl@googlemail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-13phy: intel-lgm-emmc: Add architecture dependencyGeert Uytterhoeven1-0/+1
The Intel eMMC PHY is only present on Intel Lightning Mountain SoCs. Add an architecture dependency to the PHY_INTEL_EMMC config symbol, to avoid asking the user about it when configuring a kernel for a non-x86 architecture. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200507113626.24026-3-geert+renesas@glider.be Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-13phy: ti: j721e-wiz: Fix some error return code in wiz_probe()Wei Yongjun1-1/+5
Fix to return negative error code from some error handling cases instead of 0, as done elsewhere in this function. Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Acked-by: Roger Quadros <rogerq@ti.com> Link: https://lore.kernel.org/r/20200507054109.110849-1-weiyongjun1@huawei.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-13phy: cpcap-usb: Remove some useless codeChristophe JAILLET1-2/+0
Axe a clk that is unused in the driver. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20200507203127.202197-1-christophe.jaillet@wanadoo.fr Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-13phy: samsung: s5pv210-usb2: Add delay after resetJonathan Bakker1-0/+4
The USB phy takes some time to reset, so make sure we give it to it. The delay length was taken from the 4x12 phy driver. This manifested in issues with the DWC2 driver since commit fe369e1826b3 ("usb: dwc2: Make dwc2_readl/writel functions endianness-agnostic.") where the endianness check would read the DWC ID as 0 due to the phy still resetting, resulting in the wrong endian mode being chosen. Signed-off-by: Jonathan Bakker <xc-racer2@live.ca> Link: https://lore.kernel.org/r/BN6PR04MB06605D52502816E500683553A3D10@BN6PR04MB0660.namprd04.prod.outlook.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-07phy: cadence: salvo: add salvo phy driverPeter Chen3-0/+325
Cadence SALVO PHY is a 28nm product, and is only used for USB3 & USB2. According to the Cadence, this PHY is a legacy Module, and Sierra and Torrent are later evolutions from it, and their sequence overlap is minimal, meaning we cannot reuse either (Sierra & Torrent) of the PHY drivers. Signed-off-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-05phy: qcom-qmp: Rename UFS PCS QMP v4 registersWesley Cheng2-30/+30
The UFS QMP v4 PHY has a largely different register set versus USB and PCIe. Rename the register offsets to denote that the value is specific for the UFS PCS register. Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Link: https://lore.kernel.org/r/1588636467-23409-6-git-send-email-wcheng@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-05phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USBWesley Cheng1-4/+19
The register map for SM8150 QMP USB SSPHY has moved QPHY_POWER_DOWN_CONTROL to a different offset. Allow for an offset in the register table to override default value if it is a DP capable PHY. Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Reviewed-by: Manu Gautam <mgautam@codeaurora.org> Link: https://lore.kernel.org/r/1588636467-23409-5-git-send-email-wcheng@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-05phy: qcom-qmp: Add SM8150 QMP USB3 PHY supportJack Pham2-2/+348
Add support for SM8150 QMP USB3 PHY with the necessary initialization sequences as well as additional QMP V4 register definitions. Signed-off-by: Jack Pham <jackp@codeaurora.org> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Reviewed-by: Manu Gautam <mgautam@codeaurora.org> Link: https://lore.kernel.org/r/1588636467-23409-4-git-send-email-wcheng@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-05phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCsWesley Cheng3-0/+298
This adds the SNPS FemtoPHY V2 driver used in QCOM SOCs. There are potentially multiple instances of this UTMI PHY on the SOC, all which can utilize this driver. The V2 driver will have a different register map compared to V1. Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Reviewed-by: Philipp Zabel <pza@pengutronix.de> Reviewed-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/1588636467-23409-3-git-send-email-wcheng@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-04phy: add driver for Qualcomm IPQ40xx USB PHYRobert Marko3-0/+156
Add a driver to setup the USB PHY-s on Qualcom m IPQ40xx series SoCs. The driver sets up HS and SS phys. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Link: https://lore.kernel.org/r/20200503201823.531757-1-robert.marko@sartura.hr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-04-28phy: qcom: qmp: Add SM8250 UFS PHYBjorn Andersson1-0/+3
The SM8250 UFS PHY can run off the same initialization sequence as SM8150, but add the compatible to allow future changes. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-04-24phy: ti: j721e-wiz: Implement DisplayPort mode to the wiz driverJyri Sarha1-4/+55
For DisplayPort use we need to set WIZ_CONFIG_LANECTL register's P_STANDARD_MODE bits to "mode 3". In the DisplayPort use also the P_ENABLE bits of the same register are set to P_ENABLE instead of P_ENABLE_FORCE, so that the DisplayPort driver can enable and disable the lane as needed. The DisplayPort mode is selected according to "cdns,phy-type"-properties found in link subnodes under the managed serdes (see "ti,sierra-phy-t0" and "ti,j721e-serdes-10g" devicetree bindings for details). All other values of "cdns,phy-type"-property but PHY_TYPE_DP will set P_STANDARD_MODE bits to 0 and P_ENABLE bits to force enable. Signed-off-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-04-03Merge tag 'pci-v5.7-changes' of ↵Linus Torvalds4-5/+409
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull pci updates from Bjorn Helgaas: "Enumeration: - Revert sysfs "rescan" renames that broke apps (Kelsey Skunberg) - Add more 32 GT/s link speed decoding and improve the implementation (Yicong Yang) Resource management: - Add support for sizing programmable host bridge apertures and fix a related alpha Nautilus regression (Ivan Kokshaysky) Interrupts: - Add boot interrupt quirk mechanism for Xeon chipsets and document boot interrupts (Sean V Kelley) PCIe native device hotplug: - When possible, disable in-band presence detect and use PDS (Alexandru Gagniuc) - Add DMI table for devices that don't use in-band presence detection but don't advertise that correctly (Stuart Hayes) - Fix hang when powering slots up/down via sysfs (Lukas Wunner) - Fix an MSI interrupt race (Stuart Hayes) Virtualization: - Add ACS quirks for Zhaoxin devices (Raymond Pang) Error handling: - Add Error Disconnect Recover (EDR) support so firmware can report devices disconnected via DPC and we can try to recover (Kuppuswamy Sathyanarayanan) Peer-to-peer DMA: - Add Intel Sky Lake-E Root Ports B, C, D to the whitelist (Andrew Maier) ASPM: - Reduce severity of common clock config message (Chris Packham) - Clear the correct bits when enabling L1 substates, so we don't go to the wrong state (Yicong Yang) Endpoint framework: - Replace EPF linkup ops with notifier call chain and improve locking (Kishon Vijay Abraham I) - Fix concurrent memory allocation in OB address region (Kishon Vijay Abraham I) - Move PF function number assignment to EPC core to support multiple function creation methods (Kishon Vijay Abraham I) - Fix issue with clearing configfs "start" entry (Kunihiko Hayashi) - Fix issue with endpoint MSI-X ignoring BAR Indicator and Table Offset (Kishon Vijay Abraham I) - Add support for testing DMA transfers (Kishon Vijay Abraham I) - Add support for testing > 10 endpoint devices (Kishon Vijay Abraham I) - Add support for tests to clear IRQ (Kishon Vijay Abraham I) - Add common DT schema for endpoint controllers (Kishon Vijay Abraham I) Amlogic Meson PCIe controller driver: - Add DT bindings for AXG PCIe PHY, shared MIPI/PCIe analog PHY (Remi Pommarel) - Add Amlogic AXG PCIe PHY, AXG MIPI/PCIe analog PHY drivers (Remi Pommarel) Cadence PCIe controller driver: - Add Root Complex/Endpoint DT schema for Cadence PCIe (Kishon Vijay Abraham I) Intel VMD host bridge driver: - Add two VMD Device IDs that require bus restriction mode (Sushma Kalakota) Mobiveil PCIe controller driver: - Refactor and modularize mobiveil driver (Hou Zhiqiang) - Add support for Mobiveil GPEX Gen4 host (Hou Zhiqiang) Microsoft Hyper-V host bridge driver: - Add support for Hyper-V PCI protocol version 1.3 and PCI_BUS_RELATIONS2 (Long Li) - Refactor to prepare for virtual PCI on non-x86 architectures (Boqun Feng) - Fix memory leak in hv_pci_probe()'s error path (Dexuan Cui) NVIDIA Tegra PCIe controller driver: - Use pci_parse_request_of_pci_ranges() (Rob Herring) - Add support for endpoint mode and related DT updates (Vidya Sagar) - Reduce -EPROBE_DEFER error message log level (Thierry Reding) Qualcomm PCIe controller driver: - Restrict class fixup to specific Qualcomm devices (Bjorn Andersson) Synopsys DesignWare PCIe controller driver: - Refactor core initialization code for endpoint mode (Vidya Sagar) - Fix endpoint MSI-X to use correct table address (Kishon Vijay Abraham I) TI DRA7xx PCIe controller driver: - Fix MSI IRQ handling (Vignesh Raghavendra) TI Keystone PCIe controller driver: - Allow AM654 endpoint to raise MSI-X interrupt (Kishon Vijay Abraham I) Miscellaneous: - Quirk ASMedia XHCI USB to avoid "PME# from D0" defect (Kai-Heng Feng) - Use ioremap(), not phys_to_virt(), for platform ROM to fix video ROM mapping with CONFIG_HIGHMEM (Mikel Rychliski)" * tag 'pci-v5.7-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (96 commits) misc: pci_endpoint_test: remove duplicate macro PCI_ENDPOINT_TEST_STATUS PCI: tegra: Print -EPROBE_DEFER error message at debug level misc: pci_endpoint_test: Use full pci-endpoint-test name in request_irq() misc: pci_endpoint_test: Fix to support > 10 pci-endpoint-test devices tools: PCI: Add 'e' to clear IRQ misc: pci_endpoint_test: Add ioctl to clear IRQ misc: pci_endpoint_test: Avoid using module parameter to determine irqtype PCI: keystone: Allow AM654 PCIe Endpoint to raise MSI-X interrupt PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSI-X table address PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments misc: pci_endpoint_test: Add support to get DMA option from userspace tools: PCI: Add 'd' command line option to support DMA misc: pci_endpoint_test: Use streaming DMA APIs for buffer allocation PCI: endpoint: functions/pci-epf-test: Print throughput information PCI: endpoint: functions/pci-epf-test: Add DMA support to transfer data PCI: pciehp: Fix MSI interrupt race PCI: pciehp: Fix indefinite wait on sysfs requests PCI: endpoint: Fix clearing start entry in configfs PCI: tegra: Add support for PCIe endpoint mode in Tegra194 PCI: sysfs: Revert "rescan" file renames ...
2020-03-31Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-nextLinus Torvalds1-3/+0
Pull networking updates from David Miller: "Highlights: 1) Fix the iwlwifi regression, from Johannes Berg. 2) Support BSS coloring and 802.11 encapsulation offloading in hardware, from John Crispin. 3) Fix some potential Spectre issues in qtnfmac, from Sergey Matyukevich. 4) Add TTL decrement action to openvswitch, from Matteo Croce. 5) Allow paralleization through flow_action setup by not taking the RTNL mutex, from Vlad Buslov. 6) A lot of zero-length array to flexible-array conversions, from Gustavo A. R. Silva. 7) Align XDP statistics names across several drivers for consistency, from Lorenzo Bianconi. 8) Add various pieces of infrastructure for offloading conntrack, and make use of it in mlx5 driver, from Paul Blakey. 9) Allow using listening sockets in BPF sockmap, from Jakub Sitnicki. 10) Lots of parallelization improvements during configuration changes in mlxsw driver, from Ido Schimmel. 11) Add support to devlink for generic packet traps, which report packets dropped during ACL processing. And use them in mlxsw driver. From Jiri Pirko. 12) Support bcmgenet on ACPI, from Jeremy Linton. 13) Make BPF compatible with RT, from Thomas Gleixnet, Alexei Starovoitov, and your's truly. 14) Support XDP meta-data in virtio_net, from Yuya Kusakabe. 15) Fix sysfs permissions when network devices change namespaces, from Christian Brauner. 16) Add a flags element to ethtool_ops so that drivers can more simply indicate which coalescing parameters they actually support, and therefore the generic layer can validate the user's ethtool request. Use this in all drivers, from Jakub Kicinski. 17) Offload FIFO qdisc in mlxsw, from Petr Machata. 18) Support UDP sockets in sockmap, from Lorenz Bauer. 19) Fix stretch ACK bugs in several TCP congestion control modules, from Pengcheng Yang. 20) Support virtual functiosn in octeontx2 driver, from Tomasz Duszynski. 21) Add region operations for devlink and use it in ice driver to dump NVM contents, from Jacob Keller. 22) Add support for hw offload of MACSEC, from Antoine Tenart. 23) Add support for BPF programs that can be attached to LSM hooks, from KP Singh. 24) Support for multiple paths, path managers, and counters in MPTCP. From Peter Krystad, Paolo Abeni, Florian Westphal, Davide Caratti, and others. 25) More progress on adding the netlink interface to ethtool, from Michal Kubecek" * git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (2121 commits) net: ipv6: rpl_iptunnel: Fix potential memory leak in rpl_do_srh_inline cxgb4/chcr: nic-tls stats in ethtool net: dsa: fix oops while probing Marvell DSA switches net/bpfilter: remove superfluous testing message net: macb: Fix handling of fixed-link node net: dsa: ksz: Select KSZ protocol tag netdevsim: dev: Fix memory leak in nsim_dev_take_snapshot_write net: stmmac: add EHL 2.5Gbps PCI info and PCI ID net: stmmac: add EHL PSE0 & PSE1 1Gbps PCI info and PCI ID net: stmmac: create dwmac-intel.c to contain all Intel platform net: dsa: bcm_sf2: Support specifying VLAN tag egress rule net: dsa: bcm_sf2: Add support for matching VLAN TCI net: dsa: bcm_sf2: Move writing of CFP_DATA(5) into slicing functions net: dsa: bcm_sf2: Check earlier for FLOW_EXT and FLOW_MAC_EXT net: dsa: bcm_sf2: Disable learning for ASP port net: dsa: b53: Deny enslaving port 7 for 7278 into a bridge net: dsa: b53: Prevent tagged VLAN on port 7 for 7278 net: dsa: b53: Restore VLAN entries upon (re)configuration net: dsa: bcm_sf2: Fix overflow checks hv_netvsc: Remove unnecessary round_up for recv_completion_cnt ...
2020-03-26phy: ti: gmii-sel: simplify config dependencies between net drivers and gmii phyGrygorii Strashko1-3/+0
The phy-gmii-sel can be only auto selected in Kconfig and now the pretty complex Kconfig dependencies are defined for phy-gmii-sel driver, which also need to be updated every time phy-gmii-sel is re-used for any new networking driver. Simplify Kconfig definition for phy-gmii-sel PHY driver - drop all dependencies and from networking drivers and rely on using 'imply PHY_TI_GMII_SEL' in Kconfig definitions for networking drivers instead. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Tested-by: Murali Karicheri <m-karicheri2@ti.com> Tested-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-03-21Merge tag 'phy-for-5.7' of ↵Greg Kroah-Hartman18-682/+3551
git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next Kishon writes: phy: for 5.7 *) Rename and Re-design phy-cadence-dp driver to phy-cadence-torrent driver *) Add new PHY driver for Qualcomm 28nm Hi-Speed USB PHY *) Add new PHY driver for Qualcomm Super Speed PHY in QCS404 *) Add support for Qualcomm PCIe QMP/QHP PHY in SDM845 to phy-qcom-qmp driver *) Add support for Qualcomm UFS PHY in MSM8996 to phy-qcom-qmp driver *) Add support for an additional reference clock in Mediatek phy-mtk-tphy driver *) Add support for configuring tuning parameters in Mediatek phy-mtk-tphy driver *) Add support for GMII PHY in TI K3 AM654x/J721E SoCs to phy-gmii-sel driver *) Add support for USB2 PHY in Amlogic A1 SoC Family to phy-meson-g12a-usb2 driver *) Add support for USB3/USB2/PCIe PHY in Socionext Pro5 SoC to phy-uniphier-usb3ss/phy-uniphier-usb3hs/phy-uniphier-pcie driver respectively *) Add support for QUSB2 PHY in Qualcomm SC7180 in driver *) Convert dt-bindings of Cadence DP, Qualcomm QUSB2 to YAML format Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> * tag 'phy-for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: (52 commits) phy: qcom-qusb2: Add new overriding tuning parameters in QUSB2 V2 PHY phy: qcom-qusb2: Add support for overriding tuning parameters in QUSB2 V2 PHY dt-bindings: phy: qcom-qusb2: Add support for overriding Phy tuning parameters phy: qcom-qusb2: Add generic QUSB2 V2 PHY support dt-bindings: phy: qcom,qusb2: Add compatibles for QUSB2 V2 phy and SC7180 dt-bindings: phy: qcom,qusb2: Convert QUSB2 phy bindings to yaml phy: rk-inno-usb2: Decrease verbosity of repeating log. phy: amlogic: Add Amlogic A1 USB2 PHY Driver dt-bindings: phy: Add Amlogic A1 USB2 PHY Bindings phy: ti: gmii-sel: add support for am654x/j721e soc dt-bindings: phy: ti: gmii-sel: add support for am654x/j721e soc phy: qualcomm: usb: Add SuperSpeed PHY driver dt-bindings: Add Qualcomm USB SuperSpeed PHY bindings phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driver dt-bindings: phy: Add Qualcomm Synopsys Hi-Speed USB PHY binding dt-bindings: phy: remove qcom-dwc3-usb-phy phy: phy-mtk-tphy: add a new reference clock phy: phy-mtk-tphy: remove unused u3phya_ref clock phy: phy-mtk-tphy: make the ref clock optional phy: phy-mtk-tphy: add a property for internal resistance ...
2020-03-20phy: qcom-qusb2: Add new overriding tuning parameters in QUSB2 V2 PHYSandeep Maheswaram1-0/+51
Added support for overriding bias-ctrl-value,charge-ctrl-value and hsdisc-trim-value params for QUSB2 V2 PHY Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: qcom-qusb2: Add support for overriding tuning parameters in QUSB2 V2 PHYSandeep Maheswaram1-32/+43
Added new structure for overriding tuning parameters in QUSB2 V2 PHY as the override params are increased due to usage of generic QUSB2 V2 phy table. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: qcom-qusb2: Add generic QUSB2 V2 PHY supportSandeep Maheswaram1-9/+9
Add generic QUSB2 V2 PHY table so the respective phys can use the same table. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: rk-inno-usb2: Decrease verbosity of repeating log.Christoph Muellner1-1/+1
phy-rockchip-inno-usb2 logs the message "phy-ff2c0000.syscon:usb2-phy@100.2: charger = INVALID_CHARGER" constantly with a frequency of about 1 Hz and a verbosity level of INFO. As this is clearly annoying, this patch decreases the log level to DEBUG. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: amlogic: Add Amlogic A1 USB2 PHY DriverHanjie Lin1-26/+59
This adds support for the USB2 PHY found in the Amlogic A1 SoC Family. It supports host mode only. Signed-off-by: Yue Wang <yue.wang@amlogic.com> Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: ti: gmii-sel: add support for am654x/j721e socGrygorii Strashko1-0/+19
TI AM654x/J721E SoCs have the same PHY interface selection mechanism for CPSWx subsystem as TI SoCs (AM3/4/5/DRA7), but registers and bit-fields placement is different. This patch adds corresponding support for TI AM654x/J721E SoCs PHY interface selection. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: qualcomm: usb: Add SuperSpeed PHY driverJorge Ramirez-Ortiz3-0/+256
Controls Qualcomm's SS PHY 1.0.0 implemented on various SoCs on both the 20nm and 28nm process nodes. Based on Sriharsha Allenki's <sallenki@codeaurora.org> original code. [bod: Removed dependency on extcon. Switched to gpio-usb-conn to handle VBUS On/Off Switched to usb-role-switch to bind gpio-usb-conn to DWC3] Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com> Cc: Sriharsha Allenki's <sallenki@codeaurora.org> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driverShawn Guo3-0/+427
Adds Qualcomm 28nm Hi-Speed USB PHY driver support. This PHY is usually paired with Synopsys DWC3 USB controllers on Qualcomm SoCs. The PHY can come in two flavours femtoPHY or picoPHY. This commit adds support for the femtoPHY with the possibility of extending to the picoPHY with additional future commits. Both PHYs are on a 28 nanometer process node. [bod: Updated qcom_snps_hsphy_set_mode to match new method signature Added disjunct on mode > 0 Removed regulator_set_voltage() in favour of setting floor in dts Removed 'snps' and from driver name Extended commit log to mention femtoPHY and picoPHY for future reference.] Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Jorge Ramirez-Ortiz <jorge.ramirez.ortiz@gmail.com> Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: phy-mtk-tphy: add a new reference clockChunfeng Yun1-1/+18
Usually the digital and analog phys use the same reference clock, but some platforms have two separate reference clocks for each of them, so add another optional clock to support them. In order to keep the clock names consistent with PHY IP's, change the da_ref for analog phy and ref clock for digital phy. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: phy-mtk-tphy: remove unused u3phya_ref clockChunfeng Yun1-18/+0
The u3phya_ref clock is already moved into sub-node, and renamed as ref clock, no used anymore now, so remove it, this can avoid confusion when support new platforms Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: phy-mtk-tphy: make the ref clock optionalChunfeng Yun1-1/+1
Sometimes the reference clock of USB3 PHY comes from oscillator directly, and no need refer to a fixed-clock in DTS anymore if make it optional. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: phy-mtk-tphy: add a property for internal resistanceChunfeng Yun1-2/+14
This is used to tune J-K voltage by internal R (resistance), the range is [0, 31], the resistance value is about 6.9K ohm for 0, 3.8K ohm for 31, and the step is 1K ohm Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: phy-mtk-tphy: add a property for disconnect thresholdChunfeng Yun1-2/+15
This is used to tune the threshold of disconnect, the index range is [0, 15], the threshold voltage is about 400mV for 0, 700mV for 15, and the step is 20mV. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: amlogic: G12A: Fix misuse of GENMASK macroJoe Perches1-1/+1
Arguments are supposed to be ordered high then low. Signed-off-by: Joe Perches <joe@perches.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: qcom: qmp: Use power_on/off ops for PCIeBjorn Andersson1-3/+3
The PCIe PHY initialization requires the attached device to be present, which is primarily achieved by the PCI controller driver. So move the logic from init/exit to power_on/power_off. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: John Stultz <john.stultz@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: uniphier-pcie: Add SoC-dependent phy-mode function supportKunihiko Hayashi1-7/+10
Since this phy is shared by multiple devices including USB and PCIe, it is necessary to determine which device use this phy. This patch adds SoC-dependent functions to determine a device using this phy. When there is 'socionext,syscon' property in the pcie-phy node, the driver calls SoC-dependt function instead of checking .has_syscon in SoC-dependent data. The function configures the system controller to use phy for PCIe. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: uniphier-pcie: Add legacy SoC support for Pro5Kunihiko Hayashi1-11/+72
Add legacy SoC support that needs to manage gio clock and reset and to skip setting unimplemented phy parameters. This supports Pro5. This specifies only 1 port use because Pro5 doesn't set it in the power-on sequence. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: uniphier-usb3hs: Change Rx sync mode to avoid communication failureKunihiko Hayashi1-4/+16
In case of using default parameters, communication failure might occur in rare cases. This sets Rx sync mode parameter to avoid the issue. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: uniphier-usb3hs: Add legacy SoC support for Pro5Kunihiko Hayashi1-15/+53
Add legacy SoC support that needs to manage gio clock and reset. This supports Pro5. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: uniphier-usb3ss: Add Pro5 supportKunihiko Hayashi1-0/+4
Pro5 SoC has same scheme of USB3 ss-phy as Pro4, so the data for Pro5 is equivalent to Pro4. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: socionext: Use devm_platform_ioremap_resource()Kunihiko Hayashi3-9/+3
Use devm_platform_ioremap_resource() to simplify the code. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: qcom-qmp: Add MSM8996 UFS QMP supportBjorn Andersson1-0/+106
The support for the 14nm MSM8996 UFS PHY is currently handled by the UFS-specific 14nm QMP driver, due to the earlier need for additional operations beyond the standard PHY API. Add support for this PHY to the common QMP driver, to allow us to remove the old driver. Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: cadence-torrent: Add support for subnode bindingsSwapnil Jakhade1-75/+217
Implement single link subnode support to the phy driver. Add reset support including PHY reset and individual lane reset. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: cadence-torrent: Add platform dependent initialization structureSwapnil Jakhade1-0/+9
Add platform dependent initialization data for Torrent PHY used in TI's J721E SoC. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-03-20phy: cadence-torrent: Use regmap to read and write DPTX PHY registersSwapnil Jakhade1-69/+100
Use regmap to read and write DPTX specific PHY registers. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-21 01:52:36 +0000