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2019-01-12phy: fix build breakage: add PHY_MODE_SATAJohn Hubbard1-2/+3
Commit 49e54187ae0b ("ata: libahci_platform: comply to PHY framework") uses the PHY_MODE_SATA, but that enum had not yet been added. This caused a build failure for me, with today's linux.git. Also, there is a potentially conflicting (mis-named) PHY_MODE_SATA, hiding in the Marvell Berlin SATA PHY driver. Fix the build by: 1) Renaming Marvell's defined value to a more scoped name, in order to avoid any potential conflicts: PHY_BERLIN_MODE_SATA. 2) Adding the missing enum, which was going to be added anyway as part of [1]. [1] https://lkml.kernel.org/r/20190108163124.6409-3-miquel.raynal@bootlin.com Fixes: 49e54187ae0b ("ata: libahci_platform: comply to PHY framework") Signed-off-by: John Hubbard <jhubbard@nvidia.com> Acked-by: Jens Axboe <axboe@kernel.dk> Acked-by: Olof Johansson <olof@lixom.net> Cc: Grzegorz Jaszczyk <jaz@semihalf.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2018-12-12phy: qcom-qmp: Expose provided clocks to DTEvan Green1-1/+22
Register a simple clock provider for the PHY pipe clock sources so that device tree users can point at these clocks via phandles to the lane nodes. Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Tested-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-12-12phy: qcom-qmp: Utilize fully-specified DT registersEvan Green1-13/+38
Utilize the newly fixed up DT bindings to get the tx2 and rx2 register regions for the second lane of dual-lane PHYs. Before this change, the driver was simply using lane one's register region and adding 0x400, which reached well beyond the DT-specified register allocation. This would have been a crash were it not for the page size on ARM64. Fix the driver not to rely on the magic of virtual memory by using the newly specified DT register regions for tx2 and rx2. In order to support existing device trees, this change also contains a fallback mode for when those new register regions don't exist, which reverts to the original behavior of overreaching and prints a complaint. Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-12-12phy: ti: fix semicolon.cocci warningskbuild test robot1-1/+1
drivers/phy/ti/phy-gmii-sel.c:91:2-3: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Fixes: 1811851f4e73 ("phy: ti: introduce phy-gmii-sel driver") CC: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-12-12phy: dphy: Add configuration helpersMaxime Ripard3-0/+175
The MIPI D-PHY spec defines default values and boundaries for most of the parameters it defines. Introduce helpers to help drivers get meaningful values based on their current parameters, and validate the boundaries of these parameters if needed. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-12-12phy: Add configuration interfaceMaxime Ripard1-0/+64
The phy framework is only allowing to configure the power state of the PHY using the init and power_on hooks, and their power_off and exit counterparts. While it works for most, simple, PHYs supported so far, some more advanced PHYs need some configuration depending on runtime parameters. These PHYs have been supported by a number of means already, often by using ad-hoc drivers in their consumer drivers. That doesn't work too well however, when a consumer device needs to deal with multiple PHYs, or when multiple consumers need to deal with the same PHY (a DSI driver and a CSI driver for example). So we'll add a new interface, through two funtions, phy_validate and phy_configure. The first one will allow to check that a current configuration, for a given mode, is applicable. It will also allow the PHY driver to tune the settings given as parameters as it sees fit. phy_configure will actually apply that configuration in the phy itself. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-12-12phy: add driver for Freescale i.MX8MQ USB3 PHYLi Jun5-0/+135
This is a cleaned up port of the downstream i.MX8MQ USB3 PHY driver. Signed-off-by: Li Jun <jun.li@nxp.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-12-12phy: Use of_node_name_eq for node name comparisonsRob Herring2-5/+5
Convert string compares of DT node names to use of_node_name_eq helper instead. This removes direct access to the node name pointer. For instances using of_node_cmp, this has the side effect of now using case sensitive comparisons. This should not matter for any FDT based system which all of these are. Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-12-12phy: ti: introduce phy-gmii-sel driverGrygorii Strashko3-0/+360
TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces. The interface mode is selected by configuring the MII mode selection register(s) (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and bit fields placement in SCM are different between SoCs while fields meaning is the same. Historically CPSW external Port's interface mode selection configuration was introduced using custom API and driver cpsw-phy-sel.c. This leads to unnecessary driver, DT binding and custom API support effort. This patch introduces CPSW Port's PHY Interface Mode selection Driver (phy-gmii-sel) which implements standard Linux PHY interface and used as a replacement for TI's specific driver cpsw-phy-sel.c and corresponding custom API. Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-12-12phy: mvebu-cp110-comphy: fix spelling in structure nameMiquel Raynal1-2/+2
Rename the mvebu_comhy_conf structure to be mvebu_comphy_conf, which is probably what the original author meant. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-12-12phy: mapphone-mdm6600: Improve phy related runtime PM callsTony Lindgren1-20/+51
I noticed that phy_pm_runtime_get_sync() and phy_pm_runtime_put() are not currently doing anything for phy-mapphone-mdm6600, only the sysfs interface for works for "auto" and "on". This is because of the shared GPIO pins between mdm6600 USB port and n_gsm port. We have not enabled runtime PM for the phy driver until after we've booted up mdm6600 properly to the USB mode. Otherwise phy_create() would have called pm_runtime_enable() and pm_runtime_no_callbacks() automatically on init. Let's fix this by registering the phy a bit later after we've powered up the mdm6600 USB port. And as the PM runtime support is only needed for the n_gsm mode and not for USB, we can allow the device to idle between phy_mdm6600_power_on() and phy_mdm6600_power_off(). Note that for suspend, runtime_pm is already disabled for the phy so we need to check for pm_runtime_enabled(). Cc: Johan Hovold <jhovold@gmail.com> Cc: Pavel Machek <pavel@ucw.cz> Cc: Sebastian Reichel <sre@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-12-12phy: renesas: rcar-gen3-usb2: follow the hardware manual procedureYoshihiro Shimoda1-6/+11
This patch modifies rcar_gen3_init_otg() procedure to follow Figure 73.4 of "R-Car Series, 3rd Generation User's Manual: Hardware Rev.1.00". Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-12-12phy: cadence: Add driver for Sierra PHYAlan Douglas3-1/+404
Add a Sierra PHY driver with PCIe and USB support. The PHY has multiple lanes, which can be configured into groups, and a generic PHY device is created for each group. There are two resets controlling the overall PHY block, one to enable the APB interface for programming registers, and another to enable the PHY itself. Additionally there are resets for each PHY lane. The PHY can be configured in hardware to read register settings from ROM, or they can be written by the driver. The sequence of operation on startup is to enable the APB bus, write the PHY registers (if required) for each lane group, and then enable the PHY. Each group of lanes can then be individually controlled using the power_on()/ power_off() function for that generic PHY Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-12-12phy: mvebu-cp110-comphy: convert to use eth phy mode and submodeGrygorii Strashko1-39/+51
Convert mvebu-cp110-comphy PHY driver to use recently introduced PHY_MODE_ETHERNET and phy_set_mode_ext(). Cc: Russell King - ARM Linux <linux@armlinux.org.uk> Cc: Maxime Chevallier <maxime.chevallier@bootlin.com> Cc: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-12-12phy: ocelot-serdes: convert to use eth phy mode and submodeGrygorii Strashko1-6/+16
Convert ocelot-serdes PHY driver to use recently introduced PHY_MODE_ETHERNET and phy_set_mode_ext(). Cc: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Quentin Schulz <quentin.schulz@bootlin.com> Tested-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-12-12phy: core: rework phy_set_mode to accept phy mode and submodeGrygorii Strashko15-19/+29
Currently the attempt to add support for Ethernet interface mode PHY (MII/GMII/RGMII) will lead to the necessity of extending enum phy_mode and duplicate there values from phy_interface_t enum (or introduce more PHY callbacks) [1]. Both approaches are ineffective and would lead to fast bloating of enum phy_mode or struct phy_ops in the process of adding more PHYs for different subsystems which will make them unmaintainable. As discussed in [1] the solution could be to introduce dual level PHYs mode configuration - PHY mode and PHY submode. The PHY mode will define generic PHY type (subsystem - PCIE/ETHERNET/USB_) while the PHY submode - subsystem specific interface mode. The last is usually already defined in corresponding subsystem headers (phy_interface_t for Ethernet, enum usb_device_speed for USB). This patch is cumulative change which refactors PHY framework code to support dual level PHYs mode configuration - PHY mode and PHY submode. It extends .set_mode() callback to support additional parameter "int submode" and converts all corresponding PHY drivers to support new .set_mode() callback declaration. The new extended PHY API int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode) is introduced to support dual level PHYs mode configuration and existing phy_set_mode() API is converted to macros, so PHY framework consumers do not need to be changed (~21 matches). [1] http://lkml.kernel.org/r/d63588f6-9ab0-848a-5ad4-8073143bd95d@ti.com Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-12-12phy: sun4i-usb: add support for H6 USB2 PHYIcenowy Zheng1-2/+17
The USB 2.0 PHY on Allwinner H6 SoC is similar to older Allwinner SoCs, with some USB0 quirk like A83T and PHY index 1/2 missing. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-12-12phy: sun4i-usb: add support for missing USB PHY indexIcenowy Zheng1-0/+7
The new Allwinner H6 SoC's USB2 PHY has two holes -- USB1 (which is a 3.0 port with dedicated PHY) and USB2 (which doesn't exist at all). Add support for this kind of missing USB PHY index. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-11-21phy: qcom-qusb2: Fix HSTX_TRIM tuning with fused value for SDM845Manu Gautam1-0/+1
Tune1 register on sdm845 is used to update HSTX_TRIM with fused setting. Enable same by specifying update_tune1_with_efuse flag for sdm845, otherwise driver ends up programming tune2 register. Fixes: ef17f6e212ca ("phy: qcom-qusb2: Add QUSB2 PHYs support for sdm845") Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Acked-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-11-21phy: qcom-qusb2: Use HSTX_TRIM fused value as isManu Gautam1-9/+10
Fix HSTX_TRIM tuning logic which instead of using fused value as HSTX_TRIM, incorrectly performs bitwise OR operation with existing default value. Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips") Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Acked-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-11-12phy: uniphier-pcie: Depend on HAS_IOMEMKunihiko Hayashi1-1/+2
The driver uses devm_ioremap_resource() which is only available when CONFIG_HAS_IOMEM is set, so the driver depends on this option. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-10-26Merge tag 'usb-4.20-rc1' of ↵Linus Torvalds41-196/+4006
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB/PHY updates from Greg KH: "Here is the big USB/PHY driver patches for 4.20-rc1 Lots of USB changes in here, primarily in these areas: - typec updates and new drivers - new PHY drivers - dwc2 driver updates and additions (this old core keeps getting added to new devices.) - usbtmc major update based on the industry group coming together and working to add new features and performance to the driver. - USB gadget additions for new features - USB gadget configfs updates - chipidea driver updates - other USB gadget updates - USB serial driver updates - renesas driver updates - xhci driver updates - other tiny USB driver updates All of these have been in linux-next for a while with no reported issues" * tag 'usb-4.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (229 commits) usb: phy: ab8500: silence some uninitialized variable warnings usb: xhci: tegra: Add genpd support usb: xhci: tegra: Power-off power-domains on removal usbip:vudc: BUG kmalloc-2048 (Not tainted): Poison overwritten usbip: tools: fix atoi() on non-null terminated string USB: misc: appledisplay: fix backlight update_status return code phy: phy-pxa-usb: add a new driver usb: host: add DT bindings for faraday fotg2 usb: host: ohci-at91: fix request of irq for optional gpio usb/early: remove set but not used variable 'remain_length' usb: typec: Fix copy/paste on typec_set_vconn_role() kerneldoc usb: typec: tcpm: Report back negotiated PPS voltage and current USB: core: remove set but not used variable 'udev' usb: core: fix memory leak on port_dev_path allocation USB: net2280: Remove ->disconnect() callback from net2280_pullup() usb: dwc2: disable power_down on rockchip devices usb: gadget: udc: renesas_usb3: add support for r8a77990 dt-bindings: usb: renesas_usb3: add bindings for r8a77990 usb: gadget: udc: renesas_usb3: Add r8a774a1 support USB: serial: cypress_m8: remove set but not used variable 'iflag' ...
2018-10-24Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-nextLinus Torvalds5-0/+313
Pull networking updates from David Miller: 1) Add VF IPSEC offload support in ixgbe, from Shannon Nelson. 2) Add zero-copy AF_XDP support to i40e, from Björn Töpel. 3) All in-tree drivers are converted to {g,s}et_link_ksettings() so we can get rid of the {g,s}et_settings ethtool callbacks, from Michal Kubecek. 4) Add software timestamping to veth driver, from Michael Walle. 5) More work to make packet classifiers and actions lockless, from Vlad Buslov. 6) Support sticky FDB entries in bridge, from Nikolay Aleksandrov. 7) Add ipv6 version of IP_MULTICAST_ALL sockopt, from Andre Naujoks. 8) Support batching of XDP buffers in vhost_net, from Jason Wang. 9) Add flow dissector BPF hook, from Petar Penkov. 10) i40e vf --> generic iavf conversion, from Jesse Brandeburg. 11) Add NLA_REJECT netlink attribute policy type, to signal when users provide attributes in situations which don't make sense. From Johannes Berg. 12) Switch TCP and fair-queue scheduler over to earliest departure time model. From Eric Dumazet. 13) Improve guest receive performance by doing rx busy polling in tx path of vhost networking driver, from Tonghao Zhang. 14) Add per-cgroup local storage to bpf 15) Add reference tracking to BPF, from Joe Stringer. The verifier can now make sure that references taken to objects are properly released by the program. 16) Support in-place encryption in TLS, from Vakul Garg. 17) Add new taprio packet scheduler, from Vinicius Costa Gomes. 18) Lots of selftests additions, too numerous to mention one by one here but all of which are very much appreciated. 19) Support offloading of eBPF programs containing BPF to BPF calls in nfp driver, frm Quentin Monnet. 20) Move dpaa2_ptp driver out of staging, from Yangbo Lu. 21) Lots of u32 classifier cleanups and simplifications, from Al Viro. 22) Add new strict versions of netlink message parsers, and enable them for some situations. From David Ahern. 23) Evict neighbour entries on carrier down, also from David Ahern. 24) Support BPF sk_msg verdict programs with kTLS, from Daniel Borkmann and John Fastabend. 25) Add support for filtering route dumps, from David Ahern. 26) New igc Intel driver for 2.5G parts, from Sasha Neftin et al. 27) Allow vxlan enslavement to bridges in mlxsw driver, from Ido Schimmel. 28) Add queue and stack map types to eBPF, from Mauricio Vasquez B. 29) Add back byte-queue-limit support to r8169, with all the bug fixes in other areas of the driver it works now! From Florian Westphal and Heiner Kallweit. * git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (2147 commits) tcp: add tcp_reset_xmit_timer() helper qed: Fix static checker warning Revert "be2net: remove desc field from be_eq_obj" Revert "net: simplify sock_poll_wait" net: socionext: Reset tx queue in ndo_stop net: socionext: Add dummy PHY register read in phy_write() net: socionext: Stop PHY before resetting netsec net: stmmac: Set OWN bit for jumbo frames arm64: dts: stratix10: Support Ethernet Jumbo frame tls: Add maintainers net: ethernet: ti: cpsw: unsync mcast entries while switch promisc mode octeontx2-af: Support for NIXLF's UCAST/PROMISC/ALLMULTI modes octeontx2-af: Support for setting MAC address octeontx2-af: Support for changing RSS algorithm octeontx2-af: NIX Rx flowkey configuration for RSS octeontx2-af: Install ucast and bcast pkt forwarding rules octeontx2-af: Add LMAC channel info to NIXLF_ALLOC response octeontx2-af: NPC MCAM and LDATA extract minimal configuration octeontx2-af: Enable packet length and csum validation octeontx2-af: Support for VTAG strip and capture ...
2018-10-22phy: ocelot-serdes: fix out-of-bounds readGustavo A. R. Silva1-2/+2
Currently, there is an out-of-bounds read on array ctrl->phys, once variable i reaches the maximum array size of SERDES_MAX in the for loop. Fix this by changing the condition in the for loop from i <= SERDES_MAX to i < SERDES_MAX. Addresses-Coverity-ID: 1473966 ("Out-of-bounds read") Addresses-Coverity-ID: 1473959 ("Out-of-bounds read") Fixes: 51f6b410fc22 ("phy: add driver for Microsemi Ocelot SerDes muxing") Reviewed-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-18phy: phy-pxa-usb: add a new driverLubomir Rintel3-0/+357
Turned from arch/arm/mach-mmp/devices.c into a proper PHY driver, so that in can be instantiated from a DT. Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-10-10phy: phy-ocelot-serdes: fix return value check in serdes_probe()Wei Yongjun1-2/+2
In case of error, the function syscon_node_to_regmap() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Fixes: 51f6b410fc22 ("phy: add driver for Microsemi Ocelot SerDes muxing") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-10-05phy: add driver for Microsemi Ocelot SerDes muxingQuentin Schulz5-0/+313
The Microsemi Ocelot can mux SerDes lanes (aka macros) to different switch ports or even make it act as a PCIe interface. This adds support for the muxing of the SerDes. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2018-09-26phy: renesas: convert to SPDX identifiersKuninori Morimoto2-0/+2
This patch updates license to use SPDX-License-Identifier instead of verbose license text. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-26phy: lantiq: Fix compile warningHauke Mehrtens1-1/+0
This local variable is unused, remove it. Fixes: dea54fbad332 ("phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module") Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-26phy: qcom-ufs: Declare 20nm qcom ufs qmp phy as BrokenVivek Gautam2-2/+19
Fork out separate configs for 14nm and 20nm qcom ufs qmp phys to declare the 20nm phy as broken. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-26scsi/ufs: qcom: Remove ufs_qcom_phy_*() calls from hostVivek Gautam1-1/+1
The host makes direct calls into phy using ufs_qcom_phy_*() APIs. These APIs are only defined for 20nm qcom-ufs-qmp phy which is not being used by any architecture as yet. Future architectures too are not going to use 20nm ufs phy. So remove these ufs_qcom_phy_*() calls from host to let further change declare the 20nm phy as broken. Also remove couple of stale enum defines for ufs phy. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Acked-by: Martin K. Petersen <martin.petersen@oracle.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-26phy: qcom-ufs: Remove stale methods that handle ref clkVivek Gautam1-50/+0
Remove ufs_qcom_phy_enable/(disable)_dev_ref_clk() that are not being used by any code. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-25phy: Add QMP phy based UFS phy support for sdm845Can Guo2-1/+186
Add UFS PHY support to make SDM845 UFS work with common PHY framework. Signed-off-by: Can Guo <cang@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-25phy: General struct and field cleanupCan Guo1-11/+14
Move MSM8996 specific PHY vreg list struct name to a genernal one as it is used by all PHYs. Add a specific field to handle dual lane situation. Signed-off-by: Can Guo <cang@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-25phy: Update PHY power control sequenceCan Guo1-7/+12
All PHYs should be powered on before register configuration starts. And only PCIe PHYs need an extra power control before deasserts reset state. Signed-off-by: Can Guo <cang@codeaurora.org> Reviewed-by: Manu Gautam <mgautam@codeaurora.org> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-25phy: rockchip-usb: add usb-uart setup for rk3188Heiko Stuebner1-46/+95
The rk3188 also supports bringing the uart2 out through the usb dm+dp pins, so add the necessary setup for it. rk3066 does not seem to support usb-uart functionality and this particular phy was only used on older Rockchip socs, so this leaves room for a bit of cleanup as well, as there most likely won't be new additions in the driver. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-25phy: phy-twl4030-usb: fix denied runtime accessAndreas Kemnade1-0/+29
When runtime is not enabled, pm_runtime_get_sync() returns -EACCESS, the counter will be incremented but the resume callback not called, so enumeration and charging will not start properly. To avoid that happen, disable irq on suspend and recheck on resume. Practically this happens when the device is woken up from suspend by plugging in usb. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-25phy: renesas: rcar-gen3-usb2: add is_otg_channel to use "role" sysfsYoshihiro Shimoda1-5/+18
Even if a board doesn't have otg pins connection, this hardware can change the role by a register setting. So, this patch adds "is_otg_channel" for it. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-25phy: renesas: rcar-gen3-usb2: add conditions for uses_otg_pins == falseYoshihiro Shimoda1-1/+4
If uses_otg_pins is set to false, this driver 1) should disable otg related interruptions, and 2) should not get ID pin signal, to avoid unexpected behaviors. So, this patch adds conditions for it. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-25phy: renesas: rcar-gen3-usb2: change a condition "dr_mode"Yoshihiro Shimoda1-1/+3
This patch changes a condition about dr_mode. If a device node has any dr_mode ("host", "peripheral" or "otg"), this driver allows to set "is_otg_channel" to true. Also, this patch keeps the dr_mode value for future use. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-25phy: renesas: rcar-gen3-usb2: unify OBINTEN handlingYoshihiro Shimoda1-8/+15
This patch unifies the OBINTEN handling to clean-up the code. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-25phy: renesas: rcar-gen3-usb2: Check a property to use otg pinsYoshihiro Shimoda1-18/+6
Since All R-Car Gen3 SoCs have dedicated otg pins actually but some boards don't use the otg pins (e.g. R-Car D3 Draak and R-Car E3 Ebisu), the driver should not choose SoC model base by using rcar_gen3_phy_usb2_match_table's data. So, this patch checks a "renesas,no-otg-pins" property to set the "uses_otg_pins". Note that since r8a77995-draak.dts and r8a77990-ebisu.dts don't have 'dr_mode = "otg";' for now, if we apply this patch, no behavior changes (the value of "uses_otg_pins" is false). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-25phy: renesas: rcar-gen3-usb2: Rename has_otg_pins to uses_otg_pinsYoshihiro Shimoda1-7/+7
Since R-Car E3 and D3 have dedicated otg pins actually, "has_otg_pins" is possible to misread in the future. So, this patch renames has_otg_pins to uses_otg_pins. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-25phy: renesas: rcar-gen3-usb2: fix vbus_ctrl for role sysfsYoshihiro Shimoda1-1/+1
This patch fixes and issue that the vbus_ctrl is disabled by rcar_gen3_init_from_a_peri_to_a_host(), so a usb host cannot supply the vbus. Note that this condition will exit when the otg irq happens even if we don't apply this patch. Fixes: 9bb86777fb71 ("phy: rcar-gen3-usb2: add sysfs for usb role swap") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-25phy: brcm-sata: Add BCM63138 (DSL) PHY init sequenceFlorian Fainelli1-0/+70
The BCM63138 SATA PHY requires a special initialization sequence in order to operate correctly, mostly tuning incorrect default values. Implement that sequence and match the documented compatible string as an entry point into that sequence. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-25phy: brcm-sata: allow PHY_BRCM_SATA driver to be built for DSL SoCsFlorian Fainelli1-1/+2
Broadcom ARM-based DSL SoCs (BCM63xx product line) have the same Broadcom SATA PHY that other SoCs are using, make it possible to select that driver on these platforms. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-25phy: socionext: add PCIe PHY driver supportKunihiko Hayashi3-0/+250
Add a driver for PHY interface built into PCIe controller implemented in UniPhier SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-25phy: Convert to using %pOFn instead of device_node.nameRob Herring9-22/+22
In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier. Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2018-09-13gpiolib: Pass array info to get/set array functionsJanusz Krzysztofik1-1/+3
In order to make use of array info obtained from gpiod_get_array() and speed up processing of arrays matching single GPIO chip layout, that information must be passed to get/set array functions. Extend the functions' API with that additional parameter and update all users. Pass NULL if a user builds an array itself from single GPIOs. Cc: Jonathan Corbet <corbet@lwn.net> Cc: Miguel Ojeda Sandonis <miguel.ojeda.sandonis@gmail.com> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> Cc: Lukas Wunner <lukas@wunner.de> Cc: Peter Korsgaard <peter.korsgaard@barco.com> Cc: Peter Rosin <peda@axentia.se> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Rojhalat Ibrahim <imr@rtschenk.de> Cc: Dominik Brodowski <linux@dominikbrodowski.net> Cc: Russell King <rmk+kernel@armlinux.org.uk> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Michael Hennerich <Michael.Hennerich@analog.com> Cc: Jonathan Cameron <jic23@kernel.org> Cc: Hartmut Knaack <knaack.h@gmx.de> Cc: Peter Meerwald-Stadler <pmeerw@pmeerw.net> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jiri Slaby <jslaby@suse.com> Cc: Yegor Yefremov <yegorslists@googlemail.com> Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2018-09-13gpiolib: Pass bitmaps, not integer arrays, to get/set arrayJanusz Krzysztofik1-9/+6
Most users of get/set array functions iterate consecutive bits of data, usually a single integer, while processing array of results obtained from, or building an array of values to be passed to those functions. Save time wasted on those iterations by changing the functions' API to accept bitmaps. All current users are updated as well. More benefits from the change are expected as soon as planned support for accepting/passing those bitmaps directly from/to respective GPIO chip callbacks if applicable is implemented. Cc: Jonathan Corbet <corbet@lwn.net> Cc: Miguel Ojeda Sandonis <miguel.ojeda.sandonis@gmail.com> Cc: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com> Cc: Lukas Wunner <lukas@wunner.de> Cc: Peter Korsgaard <peter.korsgaard@barco.com> Cc: Peter Rosin <peda@axentia.se> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Rojhalat Ibrahim <imr@rtschenk.de> Cc: Dominik Brodowski <linux@dominikbrodowski.net> Cc: Russell King <rmk+kernel@armlinux.org.uk> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Michael Hennerich <Michael.Hennerich@analog.com> Cc: Jonathan Cameron <jic23@kernel.org> Cc: Hartmut Knaack <knaack.h@gmx.de> Cc: Peter Meerwald-Stadler <pmeerw@pmeerw.net> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jiri Slaby <jslaby@suse.com> Cc: Yegor Yefremov <yegorslists@googlemail.com> Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-05 19:59:33 +0000