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2021-03-30phy: ti: j721e-wiz: Model the internal clocks without device tree inputKishon Vijay Abraham I1-5/+139
commit 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") modeled the internal clocks depending on the subnodes that are populated in device tree. However recent discussions in the mailing list [1] suggested to just add #clock cells in the parent DT node and model the clocks within the driver. Model the mux clocks without device tree input for AM64x SoC. Don't remove the earlier design since DT nodes for J7200 and J721e are already upstreamed. [1] -> http://lore.kernel.org/r/20210108025943.GA1790601@robh.at.kernel.org Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210310120840.16447-5-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: ti: j721e-wiz: Configure full rate divider for AM64Kishon Vijay Abraham I1-3/+36
The frequency of the txmclk between PCIe and SERDES has changed to 250MHz from 500MHz. Configure full rate divider for AM64 accordingly. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210310120840.16447-4-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: ti: j721e-wiz: Delete "clk_div_sel" clk provider during cleanupKishon Vijay Abraham I1-0/+6
commit 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") modeled both MUX clocks and DIVIDER clocks in wiz. However during cleanup, it removed only the MUX clock provider. Remove the DIVIDER clock provider here. Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210310120840.16447-3-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30phy: ti: j721e-wiz: Remove "regmap_field" from wiz_clk_{mux|div}_selKishon Vijay Abraham I1-41/+34
Both "struct wiz_clk_div_sel" and "struct wiz_clk_mux_sel" are static data that is common for all wiz instances. Including "struct regmap_field" for each of the wiz instances can yield undesirable results. Move "struct regmap_field" out of "struct wiz_clk_div_sel" and "struct wiz_clk_mux_sel" and make them point to constant data. So far no issues are observed since both these structures are not accessed outside the probe. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210310120840.16447-2-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-30drivers: phy: add support for Armada CP110 UTMI PHYKonstantin Porotchkin3-0/+393
Add support for Marvell CP110 UTMI PHY driver allowing the USB2 port configuration independently from the boot loader setup. The CP110/CP115 dies have 2 UTMI PHYs that could be connected to two USB host controllers or to single USB device controller. Since there is only one USB device controller on die, only one of the UTMI PHYs could work in USB device mode. The CONFIG_PHY_MVEBU_CP110_UTMI should be enabled for usage of this driver. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Link: https://lore.kernel.org/r/20210307163343.25684-2-kostap@marvell.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-25phy: qualcomm: remove duplicate argumentZhang Yunkai1-2/+2
'HSUSB_CTRL_DPSEHV_CLAMP' in 'val' is duplicated. Signed-off-by: Zhang Yunkai <zhang.yunkai@zte.com.cn> Link: https://lore.kernel.org/r/20210319113612.494623-1-zhang.yunkai@zte.com.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-25phy: intel: Fix a typoBhaskar Chowdhury1-1/+1
s/subsytem/subsystem/ Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com> Link: https://lore.kernel.org/r/20210320204055.26107-1-unixbhaskar@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-17phy: Add Sparx5 ethernet serdes PHY driverSteen Hegelund7-0/+5331
Add the Microchip Sparx5 ethernet serdes PHY driver for the 6G, 10G and 25G interfaces available in the Sparx5 SoC. Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20210218161451.3489955-4-steen.hegelund@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-17phy: Add media type and speed serdes configuration interfacesSteen Hegelund1-0/+30
Provide new phy configuration interfaces for media type and speed that allows e.g. PHYs used for ethernet to be configured with this information. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-By: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210218161451.3489955-3-steen.hegelund@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-15phy: phy-brcm-usb: select SOC_BRCMSTB on brcmstb onlyRafał Miłecki1-1/+1
phy-brcm-usb has some conditional init code required on selected brcmstb devices. Execution of that code depends on family / product detected by brcmstb soc code. For ARCH_BCM4908 brcmstb soc code always return 0 values as ids. Don't bother selecting & compiling that redundant driver. Depends-on: 149ae80b1d50 ("soc: bcm: brcmstb: add stubs for getting platform IDs") Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20210305152406.2588-1-zajec5@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-15phy: qcom-usb-hs: Fix fall-through warnings for ClangGustavo A. R. Silva1-0/+1
In preparation to enable -Wimplicit-fallthrough for Clang, fix a warning by explicitly adding a break statement instead of letting the code fall through to the next case. Link: https://github.com/KSPP/linux/issues/115 Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Link: https://lore.kernel.org/r/20210305100219.GA142595@embeddedor Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-15phy: ti: j721e-wiz: add missing of_node_putJunlin Yang1-0/+1
Fix OF node leaks by calling of_node_put in for_each_child_of_node when the cycle returns. Generated by: scripts/coccinelle/iterators/for_each_child.cocci Signed-off-by: Junlin Yang <yangjunlin@yulong.com> Link: https://lore.kernel.org/r/20210216082739.1414-1-angkery@163.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-15phy: rockchip-typec: add missing of_node_putJunlin Yang1-0/+1
Fix OF node leaks by calling of_node_put in for_each_available_child_of_node when the cycle returns. Generated by: scripts/coccinelle/iterators/for_each_child.cocci Signed-off-by: Junlin Yang <yangjunlin@yulong.com> Link: https://lore.kernel.org/r/20210216084847.1544-1-angkery@163.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-15phy: stm32: register usbphyc as clock provider of ck_usbo_48m clockAmelie Delaunay2-0/+66
ck_usbo_48m is generated by usbphyc PLL and used by OTG controller for Full-Speed use cases with dedicated Full-Speed transceiver. ck_usbo_48m is available as soon as the PLL is enabled. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20210208114659.15269-3-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-12phy: tusb1210: use bitmasks to set VENDOR_SPECIFIC2Liam Beguin1-13/+14
Start by reading the content of the VENDOR_SPECIFIC2 register and update each bit field based on device properties when defined. The use of bit masks prevents fields from overriding each other and enables users to clear bits which are set by default, like datapolarity in this instance. Signed-off-by: Liam Beguin <lvb@xiphos.com> Link: https://lore.kernel.org/r/20201211191241.21306-1-liambeguin@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-10Merge tag 'phy-fixes2-5.11' of ↵Greg Kroah-Hartman6-7/+20
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next Vinod writes: phy: second round of phy fixes for v5.11 - rockchip: init return and vednor prefix to dt-property - cpcap: bool conversion fix - lantiq: clock enable fix - lgm: kconfig depends on x86 - mediatek: add mising MODULE_DEVICE_TABLE() * tag 'phy-fixes2-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: phy: mediatek: Add missing MODULE_DEVICE_TABLE() phy: phy-brcm-sata: remove unneeded semicolon phy: USB_LGM_PHY should depend on X86 phy: lantiq: rcu-usb2: wait after clock enable phy: rockchip: emmc, add vendor prefix to dts properties devicetree: phy: rockchip-emmc optional add vendor prefix phy: cpcap-usb: remove unneeded conversion to bool phy: rockchip-emmc: emmc_phy_init() always return 0
2021-02-09Merge tag 'phy-for-5.12' of ↵Greg Kroah-Hartman12-122/+824
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next Vinod writes: phy-for-5.12 - Updates: - Conversion to YAML binding for: - mtk-xsphy - mtk-tphy - mtk-ufs - HDMI PHY - MIPI DSI PHY - brcmstb-usb-phy - Support for BCM4908 usb phy - Support for Qualcomm SDX55 USB and QMP phy - Support for Qualcomm SM8350 aka Snapdragon 888 UFS and USB phy - Support for Qualcomm SDM660 USB and UFS phy - Support for Qualcomm SC8180X USB and UFS phy - Support for Qualcomm IPQ6018 USB phy - Stm32 phy updates * tag 'phy-for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (41 commits) phy: cpcap-usb: Simplify bool conversion phy: qcom-qmp: make a const array static, makes object smaller phy: zynqmp: Simplify code by using dev_err_probe() phy: qcom-qmp: Add support for SM8350 UFS phy phy: qcom-qmp: Add UFS V5 registers found in SM8350 dt-bindings: phy: qcom,qmp: Add SM8350 UFS PHY bindings phy: qualcomm: usb28nm: Add MDM9607 init sequence dt-bindings: phy: qcom,qusb2: document ipq6018 compatible phy: qcom-qusb2: add QUSB2 support for IPQ6018 phy: qcom-qmp: Add SC8180X USB phy phy: qcom-qmp: Add SC8180X UFS phy dt-bindings: phy: qcom,qmp: Add SC8180X USB phy dt-bindings: phy: qcom,qmp: Add SC8180X UFS to the QMP binding dt-bindings: phy: qcom-qusb2: Document SDM660 compatible phy: qcom-qusb2: Add configuration for SDM660 phy: qcom-qusb2: Allow specifying default clock scheme dt-bindings: phy: qcom,usb-snps-femto-v2: Add SM8250 and SM8350 bindings phy: qcom-qmp: Add SM8350 USB QMP PHYs dt-bindings: phy: qcom,qmp: Add SM8150, SM8250 and SM8350 USB PHY bindings phy: qcom-qmp: Add support for SDX55 QMP PHY ...
2021-02-06phy: cpcap-usb: Simplify bool conversionYang Li1-1/+1
Fix the following coccicheck warning: ./drivers/phy/motorola/phy-cpcap-usb.c:146:31-36: WARNING: conversion to bool not needed here Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/1611905915-50394-1-git-send-email-yang.lee@linux.alibaba.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-06phy: qcom-qmp: make a const array static, makes object smallerColin Ian King1-1/+1
Don't populate the const array cfg1_settings on the stack but instead make it static. Makes the object code smaller by 24 bytes: Before: text data bss dec hex filename 73585 20240 64 93889 16ec1 drivers/phy/qualcomm/phy-qcom-qmp.o After: text data bss dec hex filename 73465 20336 64 93865 16ea9 drivers/phy/qualcomm/phy-qcom-qmp.o (gcc version 10.2.0) Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20210204180313.108876-1-colin.king@canonical.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-06phy: zynqmp: Simplify code by using dev_err_probe()Michal Simek1-7/+4
Use already prepared dev_err_probe() introduced by commit a787e5400a1c ("driver core: add device probe log helper"). It simplifies EPROBE_DEFER handling. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/0df30548f721b10475a6cc5659beda102fec3c87.1612444300.git.michal.simek@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-06phy: qcom-qmp: Add support for SM8350 UFS phyVinod Koul1-0/+127
Add the tables for init sequences for UFS QMP phy found in SM8350 SoC. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210204165805.62235-4-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-06phy: qcom-qmp: Add UFS V5 registers found in SM8350Vinod Koul1-0/+47
Add the registers for UFS found in SM8350. The UFS phy used in SM8350 seems to have same offsets as V5 phy, although Documentation for that is lacking. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210204165805.62235-3-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-04phy: mediatek: Add missing MODULE_DEVICE_TABLE()Boris Brezillon2-0/+2
This patch adds the missing MODULE_DEVICE_TABLE definitions on different Mediatek phy drivers which generates correct modalias for automatic loading when these drivers are compiled as an external module. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Link: https://lore.kernel.org/r/20210203110631.686003-1-enric.balletbo@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-04phy: phy-brcm-sata: remove unneeded semicolonYang Li1-1/+1
Eliminate the following coccicheck warning: ./drivers/phy/broadcom/phy-brcm-sata.c:654:2-3: Unneeded semicolon Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/1612321087-14743-1-git-send-email-yang.lee@linux.alibaba.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-04phy: qualcomm: usb28nm: Add MDM9607 init sequenceKonrad Dybcio1-0/+13
This is required to bring up the PHY on MDM9607-based boards. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210131013124.54484-1-konrad.dybcio@somainline.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-04phy: USB_LGM_PHY should depend on X86Geert Uytterhoeven1-0/+1
The Intel Lightning Mountain (LGM) USB3 USB is only present on Intel Lightning Mountain SoCs. Hence add a dependency on X86, to prevent asking the user about this driver when configuring a kernel without Intel Lightning Mountain platform support. Fixes: 1cce8f73a561c944 ("phy: Add USB3 PHY support for Intel LGM SoC") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210129131753.2656306-1-geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-04phy: qcom-qusb2: add QUSB2 support for IPQ6018Kathiravan T1-0/+44
Add the phy init sequence for the Super Speed ports found on IPQ6018. Signed-off-by: Kathiravan T <kathirav@codeaurora.org> [baruch: add ipq6018_regs_layout[], drop binding change] Signed-off-by: Baruch Siach <baruch@tkos.co.il> Link: https://lore.kernel.org/r/b8c22dddf1f70d89e135fe1ae705ddc68e295ebb.1611756920.git.baruch@tkos.co.il Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-04phy: qcom-qmp: Add SC8180X USB phyBjorn Andersson1-0/+3
The Qualcomm SC8180X has two QMP phys used for SuperSpeed USB, which are either the same or very similar to the same found in SM8150. Add a compatible for this, reusing the existing SM8150 USB phy config. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210121014339.1612525-2-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-04phy: qcom-qmp: Add SC8180X UFS phyBjorn Andersson1-0/+3
The UFS phy found in the Qualcomm SC8180X is either the same or very similar to the phy present in SM8150, so add a compatible and reuse the SM8150 configuration. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210120224531.1610709-2-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-19phy: qcom-qusb2: Add configuration for SDM660AngeloGioacchino Del Regno1-0/+15
The SDM660 SoC uses the same configuration as MSM8996, but the clock scheme uses a differential reference clock and none of the SoCs in this series (630, 636 and others) have got a usable PHY_CLK_SCHEME register in the TCSR for clk scheme detection. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210114174718.398638-2-angelogioacchino.delregno@somainline.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-19phy: qcom-qusb2: Allow specifying default clock schemeAngeloGioacchino Del Regno1-2/+13
The TCSR's PHY_CLK_SCHEME register is not available on all SoC models, but some may still use a differential reference clock. In preparation for these SoCs, add a se_clk_scheme_default configuration entry and declare it to true for all currently supported SoCs (retaining the previous defaults. This patch brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210114174718.398638-1-angelogioacchino.delregno@somainline.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-19phy: qcom-qmp: Add SM8350 USB QMP PHYsJack Pham2-0/+312
Add support for the USB DP & UNI PHYs found on SM8350. These use version 5.0.0 of the QMP PHY IP and thus require new "V5" definitions of the register offset macros for the QSERDES RX and TX blocks. The QSERDES common and QPHY PCS blocks' register offsets are largely unchanged from V4 so some of the existing macros can be reused. Signed-off-by: Jack Pham <jackp@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210115174723.7424-3-jackp@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-17phy: qcom-qmp: Add support for SDX55 QMP PHYManivannan Sadhasivam1-0/+83
Add support for USB3 QMP PHY found in SDX55 platform. SDX55 uses version 4.0.0 of the QMP PHY IP and doesn't make use of "com_aux" clock. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210111113010.32056-3-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-13phy: stm32: rework PLL Lock detectionAmelie Delaunay1-34/+54
USBPHYC has a register per phy to control and monitor the debug interface of the HS PHY through a digital debug access. With this register, it is possible to know if PLL Lock input to phy is high. That means the PLL is ready for HS operation. Instead of using an hard-coded delay after PLL enable and PLL disable, use this bit to ensure good operating of the HS PHY. Also use an atomic counter (n_pll_cons) to count the actual number of PLL consumers and get rid of stm32_usbphyc_has_one_phy_active. The boolean active in the usbphyc_phy structure is kept, because we need to know in remove if a phy_exit is required to properly disable the PLL. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20210105090525.23164-7-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-13phy: stm32: ensure phy are no more active when removing the driverAmelie Delaunay1-0/+6
To ensure a good balancing of regulators, and allow PLL disabling when the driver is removed, call stm32_usbphyc_phy_exit on each ports to set phys inactive and disable PLL. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20210105090525.23164-6-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-13phy: stm32: ensure pll is disabled before phys creationAmelie Delaunay1-2/+15
To ensure a good balancing of regulators, force PLL disable either by reset or by clearing the PLLEN bit. If waiting the powerdown pulse delay isn't enough, return -EPROBE_DEFER instead of polling the PLLEN bit, which will be low at the next probe. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20210105090525.23164-5-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-13phy: stm32: replace regulator_bulk* by multiple regulator_*Amelie Delaunay1-17/+52
Due to async_schedule_domain call in regulator_bulk_enable, scheduling while atomic bug can raise if regulator_bulk_enable is called under atomic context. To avoid this issue, this patch replaces all regulator_bulk* by regulator_ per regulators. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20210105090525.23164-4-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-13phy: stm32: manage 1v1 and 1v8 supplies at pll activation/deactivationAmelie Delaunay1-56/+46
PLL block requires to be powered with 1v1 and 1v8 supplies to catch ENABLE signal. Currently, supplies are managed through phy_ops .power_on/off, and PLL activation/deactivation is managed through phy_ops .init/exit. The sequence of phy_ops .power_on/.phy_init, .power_off/.exit is USB drivers dependent. To ensure a good behavior of the PLL, supplies have to be managed at PLL activation/deactivation. That means the supplies need to be put in usbphyc node and not in phy children nodes. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20210105090525.23164-3-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-13phy: phy-brcm-usb: support PHY on the BCM4908Rafał Miłecki2-1/+6
BCM4908 seems to have slightly different registers but works when programmed just like the STB one. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20210106205838.10964-3-zajec5@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-13phy: mediatek: Mark mtk_mipi_tx_driver with static keywordZou Wei1-1/+1
Fix the following sparse warning: drivers/phy/mediatek/phy-mtk-mipi-dsi.c:237:24: warning: symbol 'mtk_mipi_tx_driver' was not declared. Should it be static? Signed-off-by: Zou Wei <zou_wei@huawei.com> Link: https://lore.kernel.org/r/1610415484-92497-1-git-send-email-zou_wei@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-13phy: lantiq: rcu-usb2: wait after clock enableMathias Kresin1-1/+9
Commit 65dc2e725286 ("usb: dwc2: Update Core Reset programming flow.") revealed that the phy isn't ready immediately after enabling it's clocks. The dwc2_check_core_version() fails and the dwc2 usb driver errors out. Add a short delay to let the phy get up and running. There isn't any documentation how much time is required, the value was chosen based on tests. Signed-off-by: Mathias Kresin <dev@kresin.me> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Cc: <stable@vger.kernel.org> # v5.7+ Link: https://lore.kernel.org/r/20210107224901.2102479-1-dev@kresin.me Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-13phy: ingenic: Remove useless field .versionPaul Cercueil1-23/+0
Remove the useless field .version from the private structure, which is set but never read. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20201223124505.40792-1-paul@crapouillou.net Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-13phy: cadence-torrent: Fix error code in cdns_torrent_phy_probe()Dan Carpenter1-0/+1
This error path should return -EINVAL, but currently it returns success. Fixes: d09945eacad0 ("phy: cadence-torrent: Check total lane count for all subnodes is within limit") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/X9s7Wxq+b6ls0q7o@mwanda Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-13phy: phy-brcm-usb: specify init function format at struct levelRafał Miłecki1-4/+3
This is slightly cleaner solution that assures noone assings a wrong function to the pointer. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20201216143305.12179-2-zajec5@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-13phy: phy-brcm-usb: improve getting OF matching dataRafał Miłecki1-3/+4
1. Use of_device_get_match_data() helper to simplify the code 2. Check for NULL as a good practice Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20201216143305.12179-1-zajec5@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-13phy: rockchip: emmc, add vendor prefix to dts propertiesChris Ruehl1-2/+2
Update the implementation add "rockchip," vendor prefix for the optional dts properties. Prefix referred from vendor-prefixes.yaml. Follow up with commit 8b5c2b45b8f0a ("phy: rockchip: set pulldown for strobe line in dts") commit a8cef928276bb ("phy: rockchip-emmc: output tap delay dt property") Signed-off-by: Chris Ruehl <chris.ruehl@gtsys.com.hk> Link: https://lore.kernel.org/r/20201215014409.905-3-chris.ruehl@gtsys.com.hk Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-13phy: cpcap-usb: remove unneeded conversion to boolTian Tao1-1/+1
Fix the following warning: drivers/phy/motorola/phy-cpcap-usb.c:146:31-36: WARNING: conversion to bool not needed here. Signed-off-by: Tian Tao <tiantao6@hisilicon.com> Link: https://lore.kernel.org/r/1607598716-16108-1-git-send-email-tiantao6@hisilicon.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-13phy: rockchip-emmc: emmc_phy_init() always return 0Chris Ruehl1-3/+5
rockchip_emmc_phy_init() return variable is not set with the error value if clk_get() failed. 'emmcclk' is optional, thus use clk_get_optional() and if the return value != NULL make error processing and set the return code accordingly. Fixes: 52c0624a10cce phy: rockchip-emmc: Set phyctrl_frqsel based on card clock Signed-off-by: Chris Ruehl <chris.ruehl@gtsys.com.hk> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20201210080454.17379-1-chris.ruehl@gtsys.com.hk Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-04phy: mediatek: allow compile-testing the dsi phyArnd Bergmann1-1/+3
Randconfig builds show another broken dependency: WARNING: unmet direct dependencies detected for PHY_MTK_MIPI_DSI Depends on [n]: ARCH_MEDIATEK [=n] && OF [=y] Selected by [m]: - DRM_MEDIATEK [=m] && HAS_IOMEM [=y] && DRM [=m] && (ARCH_MEDIATEK [=n] || ARM [=y] && COMPILE_TEST [=y]) && COMMON_CLK [=y] && HAVE_ARM_SMCCC [=y] && OF [=y] && MTK_MMSYS [=y] This is similar to the hdmi driver I fixed earlier, and I guess the common-clk bug would sooner or later also manifest here, so just use the exact same solution I chose for the other driver, and hope that any future drivers just copy it from here. Fixes: 90f80d95992f ("phy: mediatek: Move mtk_mipi_dsi_phy driver into drivers/phy/mediatek folder") Fixes: f5f6e01f9164 ("phy: mediatek: allow compile-testing the hdmi phy") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210103135524.3678664-1-arnd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-01-04phy: cpcap-usb: Fix warning for missing regulator_disableTony Lindgren1-6/+13
On deferred probe, we will get the following splat: cpcap-usb-phy cpcap-usb-phy.0: could not initialize VBUS or ID IIO: -517 WARNING: CPU: 0 PID: 21 at drivers/regulator/core.c:2123 regulator_put+0x68/0x78 ... (regulator_put) from [<c068ebf0>] (release_nodes+0x1b4/0x1fc) (release_nodes) from [<c068a9a4>] (really_probe+0x104/0x4a0) (really_probe) from [<c068b034>] (driver_probe_device+0x58/0xb4) Signed-off-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20201230102105.11826-1-tony@atomide.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-30 01:55:13 +0000