summaryrefslogtreecommitdiffstats
path: root/drivers/phy
AgeCommit message (Collapse)AuthorFilesLines
2022-04-11phy: ti: tusb1210: Fix an error handling path in tusb1210_probe()Christophe JAILLET1-2/+8
tusb1210_probe_charger_detect() must be undone by a corresponding tusb1210_remove_charger_detect() in the error handling path, as already done in the remove function. Fixes: 48969a5623ed ("phy: ti: tusb1210: Add charger detection") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Link: https://lore.kernel.org/r/07c4926c42243cedb3b6067a241bb486fdda01b5.1648991162.git.christophe.jaillet@wanadoo.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-11phy: samsung: exynos5250-sata: fix missing device put in probe error pathsKrzysztof Kozlowski1-6/+14
The actions of of_find_i2c_device_by_node() in probe function should be reversed in error paths by putting the reference to obtained device. Fixes: bcff4cba41bc ("PHY: Exynos: Add Exynos5250 SATA PHY driver") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20220407091857.230386-2-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-11phy: samsung: Fix missing of_node_put() in exynos_sata_phy_probeMiaoqian Lin1-0/+1
The device_node pointer is returned by of_parse_phandle() with refcount incremented. We should use of_node_put() on it when done. Fixes: bcff4cba41bc ("PHY: Exynos: Add Exynos5250 SATA PHY driver") Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220407091857.230386-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-11phy: ti: Fix missing of_node_put in ti_pipe3_get_sysctrl()Lv Ruyi1-0/+1
of_parse_phandle() returns node pointer with refcount incremented, use of_node_put() on it to decrease refcount when done. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Lv Ruyi <lv.ruyi@zte.com.cn> Link: https://lore.kernel.org/r/20220408095617.2495234-1-lv.ruyi@zte.com.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-11phy: ti: tusb1210: Make tusb1210_chg_det_states staticHans de Goede1-1/+1
Make tusb1210_chg_det_states static, fixing the following sparse warning: drivers/phy/ti/phy-tusb1210.c:158:12: sparse: sparse: symbol 'tusb1210_chg_det_states' was not declared. Should it be static? Fixes: 48969a5623ed ("phy: ti: tusb1210: Add charger detection") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Link: https://lore.kernel.org/r/20220411135440.558394-1-hdegoede@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-03-29phy: PHY_FSL_LYNX_28G should depend on ARCH_LAYERSCAPEGeert Uytterhoeven1-2/+3
Freescale Layerscape Lynx 28G SerDes PHYs are only present on Freescale/NXP Layerscape SoCs. Move PHY_FSL_LYNX_28G outside the block for ARCH_MXC, as the latter is meant for i.MX8 SoCs, which is a different family than Layerscape. Add a dependency on ARCH_LAYERSCAPE, to prevent asking the user about this driver when configuring a kernel without Layerscape SoC support. Fixes: 02e2af20f4f9f2aa ("Merge tag 'char-misc-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc") Fixes: 8f73b37cf3fbda67 ("phy: add support for the Layerscape SerDes 28G") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2022-03-28Merge tag 'char-misc-5.18-rc1' of ↵Linus Torvalds25-234/+2711
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc and other driver updates from Greg KH: "Here is the big set of char/misc and other small driver subsystem updates for 5.18-rc1. Included in here are merges from driver subsystems which contain: - iio driver updates and new drivers - fsi driver updates - fpga driver updates - habanalabs driver updates and support for new hardware - soundwire driver updates and new drivers - phy driver updates and new drivers - coresight driver updates - icc driver updates Individual changes include: - mei driver updates - interconnect driver updates - new PECI driver subsystem added - vmci driver updates - lots of tiny misc/char driver updates All of these have been in linux-next for a while with no reported problems" * tag 'char-misc-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (556 commits) firmware: google: Properly state IOMEM dependency kgdbts: fix return value of __setup handler firmware: sysfb: fix platform-device leak in error path firmware: stratix10-svc: add missing callback parameter on RSU arm64: dts: qcom: add non-secure domain property to fastrpc nodes misc: fastrpc: Add dma handle implementation misc: fastrpc: Add fdlist implementation misc: fastrpc: Add helper function to get list and page misc: fastrpc: Add support to secure memory map dt-bindings: misc: add fastrpc domain vmid property misc: fastrpc: check before loading process to the DSP misc: fastrpc: add secure domain support dt-bindings: misc: add property to support non-secure DSP misc: fastrpc: Add support to get DSP capabilities misc: fastrpc: add support for FASTRPC_IOCTL_MEM_MAP/UNMAP misc: fastrpc: separate fastrpc device from channel context dt-bindings: nvmem: brcm,nvram: add basic NVMEM cells dt-bindings: nvmem: make "reg" property optional nvmem: brcm_nvram: parse NVRAM content into NVMEM cells nvmem: dt-bindings: Fix the error of dt-bindings check ...
2022-03-16phy: Remove duplicated include in phy-fsl-lynx-28g.cYang Li1-1/+0
Fix following includecheck warning: ./drivers/phy/freescale/phy-fsl-lynx-28g.c: linux/workqueue.h is included more than once. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/20220315235603.59481-1-yang.lee@linux.alibaba.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-03-14phy: add support for the Layerscape SerDes 28GIoana Ciornei3-0/+635
This patch adds a new generic PHY driver to support the Lynx 28G SerDes block found on some of the Layerscape SoCs such as LX2160A. At the moment, only the following Ethernet protocols are supported: SGMII/1000Base-X and 10GBaseR. SerDes lanes which are not running an Ethernet protocol or a currently supported Ethenet protocol will be left as it was configured through the RCW (Reset Configuration Word) at boot time. At probe time, the platform driver will read the current configuration of both PLLs found on a SerDes block and will determine what protocols are supported using that PLL. For example, if a PLL is configured to generate a clock net (frate) of 5GHz the only protocols sustained by that PLL are SGMII/1000Base-X (using a quarter of the full clock rate) and QSGMII using the full clock net frequency on the lane. On the .set_mode() callback, the PHY driver will first check if the requested operating mode (protocol) is even supported by the current PLL configuration and will error out if not. Then, the lane is reconfigured to run on the requested protocol. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-03-02phy: qcom-qmp: add sc8280xp UFS PHYBjorn Andersson1-0/+3
Reuse the SM8350 UFS PHY initialization sequence to add support for the same found in the Qualcomm SC8280XP platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220225035105.2294599-2-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-03-02phy: qcom-snps: Add sc8280xp supportBjorn Andersson1-0/+5
The Qualcomm sc8280xp platform comes with a 5nm femto USB PHY which, in contrast to previously seen platforms, has the SIDDQ bit in the COMMON0 register default to high. So make the driver match on the 5nm compatible and make sure to clear the SIDDQ bit on phy_init. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220225034049.2294207-2-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-03-02phy: cadence: Add Cadence D-PHY Rx driverPratyush Yadav3-0/+264
The Cadence D-PHY can be configured in Tx (DSI) mode or Rx (CSI) mode. Both modes have a different programming sequence and share little among them. In addition, a PHY configured in Tx mode cannot be used in Rx mode and vice versa. For this reason, create a separate driver for the Rx mode to make it easier to read and maintain. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20220301111621.2992275-2-p.yadav@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-25phy: marvell: phy-mvebu-a3700-comphy: Add native kernel implementationPali Rohár1-117/+1215
Remove old RPC implementation and add a new native kernel implementation. The old implementation uses ARM SMC API to issue RPC calls to ARM Trusted Firmware which provides real implementation of PHY configuration. But older versions of ARM Trusted Firmware do not provide this PHY configuration functionality, simply returning: operation not supported; or worse, some versions provide the configuration functionality incorrectly. For example the firmware shipped in ESPRESSObin board has this older version of ARM Trusted Firmware and therefore SATA, USB 3.0 and PCIe functionality do not work with newer versions of Linux kernel. Due to the above reasons, the following commits were introduced into Linux, to workaround these issues by ignoring -EOPNOTSUPP error code from phy-mvebu-a3700-comphy driver function phy_power_on(): commit 45aefe3d2251 ("ata: ahci: mvebu: Make SATA PHY optional for Armada 3720") commit 3241929b67d2 ("usb: host: xhci: mvebu: make USB 3.0 PHY optional for Armada 3720") commit b0c6ae0f8948 ("PCI: aardvark: Fix initialization with old Marvell's Arm Trusted Firmware") Replace this RPC implementation with proper native kernel implementation, which is independent on the firmware. Never return -EOPNOTSUPP for proper arguments. This should solve multiple issues with real-world boards, where it is not possible or really inconvenient to change the firmware. Let's eliminate these issues. This implementation is ported directly from Armada 3720 comphy driver found in newest version of ARM Trusted Firmware source code, but with various fixes of register names, some added comments, some refactoring due to the original code not conforming to kernel standards. Also PCIe mode poweroff support was added here, and PHY reset support. These changes are also going to be sent to ARM Trusted Firmware. [ Pali did the porting from ATF. I (Marek) then fixed some register names, some various other things, added some comments and refactored the code to kernel standards. Also fixed PHY poweroff and added PHY reset. ] Signed-off-by: Pali Rohár <pali@kernel.org> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Marek Behún <kabel@kernel.org> Link: https://lore.kernel.org/r/20220203214444.1508-3-kabel@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-25phy: marvell: phy-mvebu-a3700-comphy: Remove port from driver configurationPali Rohár1-33/+29
Port number is encoded into argument for SMC call. It is zero for SATA, PCIe and also both USB 3.0 PHYs. It is non-zero only for Ethernet PHY (incorrectly called SGMII) on lane 0. Ethernet PHY on lane 1 also uses zero port number. So construct "port" bits for SMC call argument can be constructed directly from PHY type and lane number. Change driver code to always pass zero port number for non-ethernet PHYs and for ethernet PHYs determinate port number from lane number. This simplifies the driver. As port number from DT PHY configuration is not used anymore, remove whole driver code which parses it. This also simplifies the driver. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20220203214444.1508-2-kabel@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-25phy: phy-brcm-usb: fixup BCM4908 supportRafał Miłecki3-1/+47
Just like every other family BCM4908 should get its own enum value. That is required to properly handle it in chipset conditional code. The real change is excluding BCM4908 from the PLL reprogramming code (see brcmusb_usb3_pll_54mhz()). I'm not sure what's the BCM4908 reference clock frequency but: 1. BCM4908 custom driver from Broadcom's SDK doesn't reprogram PLL 2. Doing that in Linux driver stopped PHY handling some USB 3.0 devices This change makes USB 3.0 PHY recognize e.g.: 1. 04e8:6860 - Samsung Electronics Co., Ltd Galaxy series, misc. (MTP mode) 2. 1058:259f - Western Digital My Passport 259F Broadcom's STB SoCs come with a set of SUN_TOP_CTRL_* registers that allow reading chip family and product ids. Such a block & register is missing on BCM4908 so this commit introduces "compatible" string specific binding. Fixes: 4b402fa8e0b7 ("phy: phy-brcm-usb: support PHY on the BCM4908") Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20220218172459.10431-1-zajec5@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-25phy: ti: tusb1210: Add charger detectionStephan Gerhold1-7/+370
Some Android x86 tablets with a Bay Trail (BYT) SoC and a Crystal Cove PMIC, which does not support charger-detection, rely on a TUSB1211 phy for charger-detection. Add support for charger detection on TUSB1211 phy-s and export the information about the detected charger through the standard power_supply class interface. power_supply class charger IC drivers like the bq24190_charger.c driver will then pick this up and set their input_current_limit based on this. Note the "linux,phy_charger_detect" property used to enable this is a special kernel-internal (so not part of the dt-bindings) property used by dwc3 platform code to indicate that the phy needs to do charger-detection. Changes by Hans de Goede: - Use "linux,phy_charger_detect" property to enable charger-detect - Switch from a linear flow to a state-machine, with retries on ulpi communication errors - Use SW_CONTROL bit to disable the FSM when detection is finished - Do a phy-reset on disconnect to work around the phy often refusing ulpi_read()/_write() commands after a disconnect - Use power_supply_reg_notifier() for Vbus monitoring - Export the detection result through a power_supply class device Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Co-developed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Link: https://lore.kernel.org/r/20220213130524.18748-10-hdegoede@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-25phy: ti: tusb1210: Add a delay between power-on and restoring the phy-parametersHans de Goede1-0/+5
Now that we actually log errors on ulpi_write failures it becomes clear that the ulpi_write() restoring the phy-parameters on power-on is failing after a suspend/resume add a short delay after driving the cs line high to fix this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Link: https://lore.kernel.org/r/20220213130524.18748-9-hdegoede@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-25phy: ti: tusb1210: Drop tusb->vendor_specific2 != 0 check from ↵Hans de Goede1-5/+2
tusb1210_power_on() Since commit eb445a15fa69 ("phy: tusb1210: use bitmasks to set VENDOR_SPECIFIC2") tusb->vendor_specific2 always contains a valid value so there no need to check that it is set. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Link: https://lore.kernel.org/r/20220213130524.18748-8-hdegoede@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-25phy: ti: tusb1210: Improve ulpi_read()/_write() error checkingHans de Goede1-14/+48
ulpi_read() and ulpi_write() calls can fail. Add wrapper functions to log errors when this happens and add error checking to the read + write of the phy parameters from the TUSB1210_VENDOR_SPECIFIC2 register. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Link: https://lore.kernel.org/r/20220213130524.18748-7-hdegoede@redhat.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-25phy: dphy: Correct lpx parameter and its derivatives(ta_{get,go,sure})Liu Ying1-2/+2
According to the comment of the function phy_mipi_dphy_get_default_config(), it uses minimum D-PHY timings based on MIPI D-PHY specification. They are derived from the valid ranges specified in Section 6.9, Table 14, Page 41 of the D-PHY specification (v1.2). The table 14 explicitly mentions that the minimum T-LPX parameter is 50 nanoseconds and the minimum TA-SURE parameter is T-LPX nanoseconds. Likewise, the kernel doc of the 'lpx' and 'ta_sure' members of struct phy_configure_opts_mipi_dphy mentions that the minimum values are 50000 picoseconds and @lpx picoseconds respectively. Also, the function phy_mipi_dphy_config_validate() checks if cfg->lpx is less than 50000 picoseconds and if cfg->ta_sure is less than cfg->lpx, which hints the same minimum values. Without this patch, the function phy_mipi_dphy_get_default_config() wrongly sets cfg->lpx to 60000 picoseconds and cfg->ta_sure to 2 * cfg->lpx. So, let's correct them to 50000 picoseconds and cfg->lpx respectively. Note that I've only tested the patch with RM67191 DSI panel on i.MX8mq EVK. Help is needed to test with other i.MX8mq, Meson and Rockchip platforms, as I don't have the hardwares. Fixes: dddc97e82303 ("phy: dphy: Add configuration helpers") Cc: Andrzej Hajda <andrzej.hajda@intel.com> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Vinod Koul <vkoul@kernel.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Maxime Ripard <mripard@kernel.org> Cc: Guido Günther <agx@sigxcpu.org> Signed-off-by: Liu Ying <victor.liu@nxp.com> Link: https://lore.kernel.org/r/20220216071257.1647703-1-victor.liu@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-25phy: usb: Add "wake on" functionality for newer Synopsis XHCI controllersAl Cooper1-8/+38
Add "wake on" support for the newer Synopsis based XHCI only controller. This works on the 72165 and 72164 and newer chips and does not work on 7216 based systems. Also switch the USB sysclk to a slower clock on suspend to save additional power in S2. The clock switch will only save power on the 72165b0 and newer chips and is a nop on older chips. Signed-off-by: Al Cooper <alcooperx@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20220215032422.5179-1-f.fainelli@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-25phy/cadence: Use of_device_get_match_data()Minghao Chi (CGEL ZTE)1-6/+1
Use of_device_get_match_data() instead of open-coding it. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: Minghao Chi (CGEL ZTE) <chi.minghao@zte.com.cn> Link: https://lore.kernel.org/r/20220214020626.1714696-1-chi.minghao@zte.com.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-25phy: sun4i-usb: Add D1 variantSamuel Holland1-0/+10
D1 has a register layout like A100 and H616, with the moved SIDDQ bit. Unlike H616 it does not have any dependencies between PHY instances. Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220203013558.11490-4-samuel@sholland.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-25phy: sun4i-usb: Rework HCI PHY (aka "pmu_unk1") handlingAndre Przywara1-17/+13
As Icenowy pointed out, newer manuals (starting with H6) actually document the register block at offset 0x800 as "HCI controller and PHY interface", also describe the bits in our "PMU_UNK1" register. Let's put proper names to those "unknown" variables and symbols. While we are at it, generalise the existing code by allowing a bitmap of bits to clear and set, to cover newer SoCs: The A100 and H616 use a different bit for the SIDDQ control. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220203013558.11490-3-samuel@sholland.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-25phy: sun4i-usb: Remove .disc_thresh where not applicableSamuel Holland1-1/+0
.disc_thresh is not used when .type = sun50i_h6_phy, so providing a value for it is misleading. Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220203013558.11490-2-samuel@sholland.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-24phy: rockchip: add naneng combo phy for RK3568Yifeng Zhao3-0/+590
This patch implements a combo phy driver for Rockchip SoCs with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy, sata-phy or sgmii-phy. Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Frank Wunderlich <frank-w@public-files.de> Link: https://lore.kernel.org/r/20220208091326.12495-4-yifeng.zhao@rock-chips.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-08phy: qcom: Program SSC only if supported by sinkSankeerth Billakanti1-3/+5
Some legacy eDP sinks may not support SSC. The support for SSC is indicated through an opts flag from the controller driver. This change will enable SSC only if the sink supports it. Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20220207161612.REPOST.v1.3.Ie81d594ec2327dae6410db359cc492484bab171f@changeid Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-08phy: qcom: Add support for eDP PHY on sc7280Sankeerth Billakanti1-0/+1
The sc7280 platform supports native eDP controller and PHY. This change will add support for the eDP PHY on sc7280. Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20220207161612.REPOST.v1.2.Iff75c0ea8499f0baf2aa5800f2c45c4128e2415a@changeid Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-07phy: cadence: Sierra: Add support for skipping configurationAswath Govindraju1-25/+57
In some cases, a single SerDes instance can be shared between two different processors, each using a separate link. In these cases, the SerDes configuration is done in an earlier boot stage. Therefore, add support to skip reconfiguring, if it is was already configured beforehand. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20220128072642.29188-1-a-govindraju@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-07Merge tag 'phy-fixes-5.17' into nextVinod Koul10-27/+75
Merge phy fixes for 5.17 into next branch to resolve the conflict between fixes and next for upcoming patches
2022-02-02phy: dphy: Correct clk_pre parameterLiu Ying3-4/+6
The D-PHY specification (v1.2) explicitly mentions that the T-CLK-PRE parameter's unit is Unit Interval(UI) and the minimum value is 8. Also, kernel doc of the 'clk_pre' member of struct phy_configure_opts_mipi_dphy mentions that it should be in UI. However, the dphy core driver wrongly sets 'clk_pre' to 8000, which seems to hint that it's in picoseconds. So, let's fix the dphy core driver to correctly reflect the T-CLK-PRE parameter's minimum value according to the D-PHY specification. I'm assuming that all impacted custom drivers shall program values in TxByteClkHS cycles into hardware for the T-CLK-PRE parameter. The D-PHY specification mentions that the frequency of TxByteClkHS is exactly 1/8 the High-Speed(HS) bit rate(each HS bit consumes one UI). So, relevant custom driver code is changed to program those values as DIV_ROUND_UP(cfg->clk_pre, BITS_PER_BYTE), then. Note that I've only tested the patch with RM67191 DSI panel on i.MX8mq EVK. Help is needed to test with other i.MX8mq, Meson and Rockchip platforms, as I don't have the hardwares. Fixes: 2ed869990e14 ("phy: Add MIPI D-PHY configuration options") Tested-by: Liu Ying <victor.liu@nxp.com> # RM67191 DSI panel on i.MX8mq EVK Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> # for phy-meson-axg-mipi-dphy.c Tested-by: Neil Armstrong <narmstrong@baylibre.com> # for phy-meson-axg-mipi-dphy.c Tested-by: Guido Günther <agx@sigxcpu.org> # Librem 5 (imx8mq) with it's rather picky panel Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> Link: https://lore.kernel.org/r/20220124024007.1465018-1-victor.liu@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-27phy: phy-mtk-tphy: Fix duplicated argument in phy-mtk-tphyWan Jiabing1-1/+1
Fix following coccicheck warning: ./drivers/phy/mediatek/phy-mtk-tphy.c:994:6-29: duplicated argument to && or || The efuse_rx_imp is duplicate. Here should be efuse_tx_imp. Signed-off-by: Wan Jiabing <wanjiabing@vivo.com> Acked-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20220107025050.787720-1-wanjiabing@vivo.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-27phy: amlogic: meson8b-usb2: fix shared reset control useAmjad Ouled-Ameur1-0/+4
Use reset_control_rearm() call if an error occurs in case phy_meson8b_usb2_power_on() fails after reset() has been called, or in case phy_meson8b_usb2_power_off() is called i.e the resource is no longer used and the reset line may be triggered again by other devices. reset_control_rearm() keeps use of triggered_count sane in the reset framework, use of reset_control_reset() on shared reset line should be balanced with reset_control_rearm(). Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com> Reported-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220111095255.176141-4-aouledameur@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-27phy: amlogic: meson8b-usb2: Use dev_err_probe()Amjad Ouled-Ameur1-2/+3
Use the existing dev_err_probe() helper instead of open-coding the same operation. Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com> Reported-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220111095255.176141-3-aouledameur@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-27phy: amlogic: phy-meson-gxl-usb2: fix shared reset controller useAmjad Ouled-Ameur1-1/+4
Use reset_control_rearm() call if an error occurs in case phy_meson_gxl_usb2_init() fails after reset() has been called ; or in case phy_meson_gxl_usb2_exit() is called i.e the resource is no longer used and the reset line may be triggered again by other devices. reset_control_rearm() keeps use of triggered_count sane in the reset framework. Therefore, use of reset_control_reset() on shared reset line should be balanced with reset_control_rearm(). Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com> Reported-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220111095255.176141-2-aouledameur@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-27phy: freescale: i.MX8 PHYs should depend on ARCH_MXC && ARM64Geert Uytterhoeven1-0/+5
The Freescale/NXP i.MX8 USB3, MIPI DSI, and PCIE PHYs are only present on the NXP i.MX8 family of SoCs. Hence wrap the config symbols for these PHYs inside a check for ARCH_MXC && ARM64, to prevent asking the user about these drivers when configuring a kernel without NXP i.MX SoC family support. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Guido Günther <agx@sigxcpu.org> Link: https://lore.kernel.org/r/393868affd830016d35f0d9aba32ccd7098c8073.1641987369.git.geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-27phy: stm32: fix a refcount leak in stm32_usbphyc_pll_enable()Dan Carpenter1-1/+1
This error path needs to decrement "usbphyc->n_pll_cons.counter" before returning. Fixes: 5b1af71280ab ("phy: stm32: rework PLL Lock detection") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20220112111724.GB3019@kili Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-27phy: qcom-qusb2: Add compatible for MSM8953Luca Weiss1-0/+3
Add compatible for MSM8953 QUSB2 device which reuses MSM8996 configuration. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Acked-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20220112194118.178026-3-luca@z3ntu.xyz Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-27phy: freescale: pcie: cosmetic clean-upMarcel Ziswiler1-1/+2
Sort includes alphabethically and add a new line before the dt-bindings one as usually done. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Link: https://lore.kernel.org/r/20220113090321.119880-1-marcel@ziswiler.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-27phy: xilinx: zynqmp: Fix bus width setting for SGMIIRobert Hancock1-5/+6
TX_PROT_BUS_WIDTH and RX_PROT_BUS_WIDTH are single registers with separate bit fields for each lane. The code in xpsgtr_phy_init_sgmii was not preserving the existing register value for other lanes, so enabling the PHY in SGMII mode on one lane zeroed out the settings for all other lanes, causing other PS-GTR peripherals such as USB3 to malfunction. Use xpsgtr_clr_set to only manipulate the desired bits in the register. Fixes: 4a33bea00314 ("phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver") Signed-off-by: Robert Hancock <robert.hancock@calian.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20220126001600.1592218-1-robert.hancock@calian.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-24drivers: phy: qcom: ipq806x-usb: conver latch function to pool macroAnsuel Smith1-12/+5
Convert latch function to readl pool macro to tidy things up. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20220117002641.26773-2-ansuelsmth@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-24drivers: phy: qcom: ipq806x-usb: convert to BITFIELD macroAnsuel Smith1-5/+6
Convert some define to BITFIELD macro to tidy things up. Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20220117002641.26773-1-ansuelsmth@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-24phy: cadence: Sierra: fix error handling bugs in probe()Dan Carpenter1-14/+21
There are two bugs in the error handling: 1: If devm_of_phy_provider_register() fails then there was no cleanup. 2: The error handling called of_node_put(child) improperly leading to a use after free. We are only holding the reference inside the loop so the last two gotos after the loop lead to a use after free bug. Fix this by cleaning up the partial allocations (or partial iterations) in the loop before doing the goto. Fixes: a43f72ae136a ("phy: cadence: Sierra: Change MAX_LANES of Sierra to 16") Fixes: 44d30d622821 ("phy: cadence: Add driver for Sierra PHY") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20220115115146.GC7552@kili Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-24phy: ti: Fix missing sentinel for clk_div_tableKishon Vijay Abraham I1-0/+1
_get_table_maxdiv() tries to access "clk_div_table" array out of bound defined in phy-j721e-wiz.c. Add a sentinel entry to prevent the following global-out-of-bounds error reported by enabling KASAN. [ 9.552392] BUG: KASAN: global-out-of-bounds in _get_maxdiv+0xc0/0x148 [ 9.558948] Read of size 4 at addr ffff8000095b25a4 by task kworker/u4:1/38 [ 9.565926] [ 9.567441] CPU: 1 PID: 38 Comm: kworker/u4:1 Not tainted 5.16.0-116492-gdaadb3bd0e8d-dirty #360 [ 9.576242] Hardware name: Texas Instruments J721e EVM (DT) [ 9.581832] Workqueue: events_unbound deferred_probe_work_func [ 9.587708] Call trace: [ 9.590174] dump_backtrace+0x20c/0x218 [ 9.594038] show_stack+0x18/0x68 [ 9.597375] dump_stack_lvl+0x9c/0xd8 [ 9.601062] print_address_description.constprop.0+0x78/0x334 [ 9.606830] kasan_report+0x1f0/0x260 [ 9.610517] __asan_load4+0x9c/0xd8 [ 9.614030] _get_maxdiv+0xc0/0x148 [ 9.617540] divider_determine_rate+0x88/0x488 [ 9.622005] divider_round_rate_parent+0xc8/0x124 [ 9.626729] wiz_clk_div_round_rate+0x54/0x68 [ 9.631113] clk_core_determine_round_nolock+0x124/0x158 [ 9.636448] clk_core_round_rate_nolock+0x68/0x138 [ 9.641260] clk_core_set_rate_nolock+0x268/0x3a8 [ 9.645987] clk_set_rate+0x50/0xa8 [ 9.649499] cdns_sierra_phy_init+0x88/0x248 [ 9.653794] phy_init+0x98/0x108 [ 9.657046] cdns_pcie_enable_phy+0xa0/0x170 [ 9.661340] cdns_pcie_init_phy+0x250/0x2b0 [ 9.665546] j721e_pcie_probe+0x4b8/0x798 [ 9.669579] platform_probe+0x8c/0x108 [ 9.673350] really_probe+0x114/0x630 [ 9.677037] __driver_probe_device+0x18c/0x220 [ 9.681505] driver_probe_device+0xac/0x150 [ 9.685712] __device_attach_driver+0xec/0x170 [ 9.690178] bus_for_each_drv+0xf0/0x158 [ 9.694124] __device_attach+0x184/0x210 [ 9.698070] device_initial_probe+0x14/0x20 [ 9.702277] bus_probe_device+0xec/0x100 [ 9.706223] deferred_probe_work_func+0x124/0x180 [ 9.710951] process_one_work+0x4b0/0xbc0 [ 9.714983] worker_thread+0x74/0x5d0 [ 9.718668] kthread+0x214/0x230 [ 9.721919] ret_from_fork+0x10/0x20 [ 9.725520] [ 9.727032] The buggy address belongs to the variable: [ 9.732183] clk_div_table+0x24/0x440 Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Cc: stable@vger.kernel.org # v5.10+ Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20220117110108.4117-1-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-23phy: broadcom: Kconfig: Fix PHY_BRCM_USB config optionAl Cooper1-2/+1
The previous commit 4b402fa8e0b7 ("phy: phy-brcm-usb: support PHY on the BCM4908") added a second "default" line for ARCH_BCM_4908 above the original "default" line for ARCH_BRCMSTB. When two "default" lines are used, only the first is used and this change stopped the PHY_BRCM_USB option for being enabled for ARCH_BRCMSTB. The fix is to use one "default line with "||". Fixes: 4b402fa8e0b7 ("phy: phy-brcm-usb: support PHY on the BCM4908") Signed-off-by: Al Cooper <alcooperx@gmail.com> Acked-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20211201180653.35097-4-alcooperx@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-23phy: usb: Leave some clocks running during suspendAl Cooper1-0/+38
The PHY client driver does a phy_exit() call on suspend or rmmod and the PHY driver needs to know the difference because some clocks need to be kept running for suspend but can be shutdown on unbind/rmmod (or if there are no PHY clients at all). The fix is to use a PM notifier so the driver can tell if a PHY client is calling exit() because of a system suspend or a driver unbind/rmmod. Signed-off-by: Al Cooper <alcooperx@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20211201180653.35097-2-alcooperx@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-14Merge tag 'char-misc-5.17-rc1' of ↵Linus Torvalds35-582/+4953
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc and other driver updates from Greg KH: "Here is the large set of char, misc, and other "small" driver subsystem changes for 5.17-rc1. Lots of different things are in here for char/misc drivers such as: - habanalabs driver updates - mei driver updates - lkdtm driver updates - vmw_vmci driver updates - android binder driver updates - other small char/misc driver updates Also smaller driver subsystems have also been updated, including: - fpga subsystem updates - iio subsystem updates - soundwire subsystem updates - extcon subsystem updates - gnss subsystem updates - phy subsystem updates - coresight subsystem updates - firmware subsystem updates - comedi subsystem updates - mhi subsystem updates - speakup subsystem updates - rapidio subsystem updates - spmi subsystem updates - virtual driver updates - counter subsystem updates Too many individual changes to summarize, the shortlog contains the full details. All of these have been in linux-next for a while with no reported issues" * tag 'char-misc-5.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (406 commits) counter: 104-quad-8: Fix use-after-free by quad8_irq_handler dt-bindings: mux: Document mux-states property dt-bindings: ti-serdes-mux: Add defines for J721S2 SoC counter: remove old and now unused registration API counter: ti-eqep: Convert to new counter registration counter: stm32-lptimer-cnt: Convert to new counter registration counter: stm32-timer-cnt: Convert to new counter registration counter: microchip-tcb-capture: Convert to new counter registration counter: ftm-quaddec: Convert to new counter registration counter: intel-qep: Convert to new counter registration counter: interrupt-cnt: Convert to new counter registration counter: 104-quad-8: Convert to new counter registration counter: Update documentation for new counter registration functions counter: Provide alternative counter registration functions counter: stm32-timer-cnt: Convert to counter_priv() wrapper counter: stm32-lptimer-cnt: Convert to counter_priv() wrapper counter: ti-eqep: Convert to counter_priv() wrapper counter: ftm-quaddec: Convert to counter_priv() wrapper counter: intel-qep: Convert to counter_priv() wrapper counter: microchip-tcb-capture: Convert to counter_priv() wrapper ...
2021-12-30Merge tag 'phy-for-5.17' of ↵Greg Kroah-Hartman35-582/+4953
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next Vinod writes: phy-for-5.17 - New support: - Qualcomm eDP PHY driver - Qualcomm SM8450 UFS, USB2, USB3, PCIe0 and PCIe1 phy support - Lan966x ethernet serdes PHY driver - Support for uniphier NXI & Pro4 SoC - Qualcomm SM6350 USB2 support - Amlogic Meson8 HDMI TX PHY driver - Rockchip rk3568 usb2 support - Intel Thunder Bay eMMC PHY driver - Freescale IMX8 PCIe phy driver - Updates: - Cadence Sierra driver updates for multilink configurations - Bcm usb2 updates for Phy reg space * tag 'phy-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (72 commits) phy: cadence: Sierra: Add support for derived reference clock output dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration phy: cadence: Sierra: Add support for PHY multilink configurations phy: cadence: Sierra: Fix to get correct parent for mux clocks phy: cadence: Sierra: Update single link PCIe register configuration phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation phy: cadence: Sierra: Check cmn_ready assertion during PHY power on phy: cadence: Sierra: Add PHY PCS common register configurations phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation phy: cadence: Sierra: Add support to get SSC type from device tree dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic names phy: cadence: Sierra: Prepare driver to add support for multilink configurations phy: cadence: Sierra: Use of_device_get_match_data() to get driver data phy: mediatek: Fix missing check in mtk_mipi_tx_probe phy: uniphier-usb3ss: fix unintended writing zeros to PHY register phy: phy-mtk-tphy: use new io helpers to access register phy: phy-mtk-xsphy: use new io helpers to access register phy: mediatek: add helpers to update bits of registers ...
2021-12-27phy: cadence: Sierra: Add support for derived reference clock outputSwapnil Jakhade1-1/+108
Sierra has derived differential reference clock output which is sourced after the spread spectrum generation has been added. Add support to drive derived reference clock out of serdes. Model this derived clock as a "clock" so that platforms using this can enable it. Sierra Main LC VCO PLL divider 1 clock is programmed to output 100MHz clock output. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-16-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configurationSwapnil Jakhade1-1/+376
Add register sequences for PCIe + QSGMII PHY multilink configuration. PHY configuration for multi-link operation is done in two steps. e.g. Consider a case for a 4 lane PHY with PCIe using 2 lanes and QSGMII other 2 lanes. Sierra PHY has 2 PLLs, viz. PLLLC and PLLLC1. So in this case, PLLLC is used for PCIe and PLLLC1 is used for QSGMII. PHY is configured in two steps as described below. [1] For first step, the register values are selected as [TYPE_PCIE][TYPE_QSGMII][ssc]. This will configure PHY registers associated for PCIe involving PLLLC registers and registers for first 2 lanes of PHY. [2] In second step, the register values are selected as [TYPE_QSGMII][TYPE_PCIE][ssc]. This will configure PHY registers associated for QSGMII involving PLLLC1 registers and registers for other 2 lanes of PHY. This completes the PHY configuration for multilink operation. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-14-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-29 06:47:38 +0000