summaryrefslogtreecommitdiffstats
path: root/drivers/phy
AgeCommit message (Collapse)AuthorFilesLines
2019-05-08Merge tag 'usb-5.2-rc1' of ↵Linus Torvalds39-310/+4464
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB/PHY updates from Greg KH: "Here is the big set of USB and PHY driver patches for 5.2-rc1 There is the usual set of: - USB gadget updates - PHY driver updates and additions - USB serial driver updates and fixes - typec updates and new chips supported - mtu3 driver updates - xhci driver updates - other tiny driver updates Nothing really interesting, just constant forward progress. All of these have been in linux-next for a while with no reported issues. The usb-gadget and usb-serial trees were merged a bit "late", but both of them had been in linux-next before they got merged here last Friday" * tag 'usb-5.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (206 commits) USB: serial: f81232: implement break control USB: serial: f81232: add high baud rate support USB: serial: f81232: clear overrun flag USB: serial: f81232: fix interrupt worker not stop usb: dwc3: Rename DWC3_DCTL_LPM_ERRATA usb: dwc3: Fix default lpm_nyet_threshold value usb: dwc3: debug: Print GET_STATUS(device) tracepoint usb: dwc3: Do core validation early on probe usb: dwc3: gadget: Set lpm_capable usb: gadget: atmel: tie wake lock to running clock usb: gadget: atmel: support USB suspend usb: gadget: atmel_usba_udc: simplify setting of interrupt-enabled mask dwc2: gadget: Fix completed transfer size calculation in DDMA usb: dwc2: Set lpm mode parameters depend on HW configuration usb: dwc2: Fix channel disable flow usb: dwc2: Set actual frame number for completed ISOC transfer usb: gadget: do not use __constant_cpu_to_le16 usb: dwc2: gadget: Increase descriptors count for ISOC's usb: introduce usb_ep_type_string() function usb: dwc3: move synchronize_irq() out of the spinlock protected block ...
2019-04-25Merge tag 'phy-for-5.1-rc-v2' of ↵Greg Kroah-Hartman8-31/+28
git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into char-misc-next Kishon writes: phy: for 5.1-rc *) Fix sun4i-usb PHY driver to get USB gadget working on H3/R40/V3/V3s *) Fix cable state handling in phy-twl4030-usb driver to get rid of regulator_put() warning *) Fix linker errors and compilation warnings got with randconfig *) Fix sparse warnings and .cocci warnings Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> * tag 'phy-for-5.1-rc-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: phy: sun4i-usb: Make sure to disable PHY0 passby for peripheral mode phy: fix platform_no_drv_owner.cocci warnings phy: mapphone-mdm6600: add gpiolib dependency phy: ti: usb2: fix OMAP_CONTROL_PHY dependency phy: allwinner: allow compile testing phy: qcom-ufs: Make ufs_qcom_phy_disable_iface_clk static phy: rockchip-typec: Make usb3_pll_cfg and dp_pll_cfg static phy: phy-twl4030-usb: Fix cable state handling
2019-04-25Merge tag 'phy-for-5.2' of ↵Greg Kroah-Hartman39-310/+4464
git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next Kishon writes: phy: for 5.2 *) Add a new *release* phy_ops invoked when the consumer relinquishes PHY that can be used to undo the operation performed in xlate *) Add new driver to support USB2 PHY and shared USB3 + PCIE PHY in Amlogic G12A SoC Family. *) Add new driver to support for Broadcom's Stingray USB PHY (Type 1 has one super speed PHY and one high speed PHY, Type 2 has one high speed PHY) *) Add new driver to support USB PHY in hi3660 SoC of Hisilicon *) Add new driver to support UFS M-PHY in MediaTek SoC *) Add new driver to support XUSB pad controller in Tegra186 SoCs *) Add new driver to support SERDES in TI's AM654 platform *) Add support for generation 2 USB2 PHY and gneration 3 USB2 PHY in r8a77470 to phy-rcar-gen2.c and phy-rcar-gen3-usb2.c respectively *) Add support for PCIe QMP PHY support in msm8998 to phy-qcom-qmp.c *) Add support for SERDES6G in phy-ocelot-serdes.c *) Add support to set drive impedance from device tree in phy-rockchip-emmc.c *) Add support to power up/down the VBUS voltage rail in phy-fsl-imx8mq-usb.c *) Add support to shut off regulators that power UFS during system suspend *) Re-design phy-rcar-gen3-usb2.c to create separate PHY instances for each channel which helps to enable/disable interrupts for each instance independently *) Fix PCIe power up sequence to follow the TRM in order to ensure the DPLL & PHY operates correctly over the entire temperature range. *) Use devm_clk_get_optional to get optional clocks instead of adding custom error checks Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> * tag 'phy-for-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: (51 commits) dt-bindings: phy-qcom-qmp: Tweak qcom,msm8998-qmp-ufs-phy dt-bindings: phy-qcom-qmp: Add qcom,msm8998-qmp-pcie-phy phy: Add usb phy support for hi3660 Soc of Hisilicon dt-bindings: phy: Add support for HiSilicon's hi3660 USB PHY scsi: phy: mediatek: fix typo in author's email address phy: ocelot-serdes: Add support for SERDES6G muxing phy: fsl-imx8mq-usb: add support for VBUS power control dt-bindings: phy-imx8mq-usb: add optional vbus supply regulator phy: qcom-qmp: Add msm8998 PCIe QMP PHY support phy: ti: am654-serdes: Support all clksel values phy: ti: Add a new SERDES driver for TI's AM654x SoC dt-bindings: phy: ti: Add dt binding documentation for SERDES in AM654x SoC phy: core: Invoke pm_runtime_get_*/pm_runtime_put_* before invoking reset callback phy: core: Add *release* phy_ops invoked when the consumer relinquishes PHY phy: phy-meson-gxl-usb2: get optional clock by devm_clk_get_optional() phy: socionext: get optional clock by devm_clk_get_optional() phy: qcom-qusb2: get optional clock by devm_clk_get_optional() phy: phy-mtk-tphy: get optional clock by devm_clk_get_optional() phy: renesas: rcar-gen3-usb2: enable/disable independent irqs phy: renesas: rcar-gen3-usb2: Use pdev's device pointer on dev_vdbg() ...
2019-04-18phy: Add usb phy support for hi3660 Soc of HisiliconYu Chen3-0/+244
This driver handles usb phy power on and shutdown for hi3660 Soc of Hisilicon. Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Mauro Carvalho Chehab <mchehab+samsung@kernel.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Pengcheng Li <lpc.li@hisilicon.com> Cc: Jianguo Sun <sunjianguo1@huawei.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Jiancheng Xue <xuejiancheng@hisilicon.com> Cc: John Stultz <john.stultz@linaro.org> Cc: Binghui Wang <wangbinghui@hisilicon.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Yu Chen <chenyu56@huawei.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-18scsi: phy: mediatek: fix typo in author's email addressColin Ian King1-1/+1
There is a typo in the module author's email address. Fix this. Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Stanley Chu <stanley.chu@mediatek.com> Acked-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-18phy: ocelot-serdes: Add support for SERDES6G muxingKavya Sree Kotagiri1-2/+238
Adding support for SERDES6G muxing required for QSGMII mode of operation. Signed-off-by: Kavya Sree Kotagiri <kavyasree.kotagiri@microchip.com> Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: Steen Hegelund <Steen.Hegelund@microchip.com> Co-developed-by: Quentin Schulz <quentin.schulz@bootlin.com> Co-developed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-18phy: fsl-imx8mq-usb: add support for VBUS power controlLucas Stach1-0/+12
This adds support to the PHY driver to power up/down the VBUS voltage rail at the appropriate times. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: qcom-qmp: Add msm8998 PCIe QMP PHY supportMarc Gonzalez2-0/+122
Documentation for this PHY, and the proper configuration settings, is *not* publicly available. Therefore the initialization sequence is copied wholesale from downstream: https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm8998-v2.dtsi?h=LE.UM.1.3.r3.25#n372 Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: ti: am654-serdes: Support all clksel valuesRoger Quadros1-49/+83
Add support to select all 16 CLKSEL combinations that are shown in "SerDes Reference Clock Distribution" in AM65 TRM. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: ti: Add a new SERDES driver for TI's AM654x SoCKishon Vijay Abraham I3-0/+637
Add a new SERDES driver for TI's AM654x SoC which configures the SERDES only for PCIe. Support fo USB3 will be added later. SERDES in am654x has three input clocks (left input, externel reference clock and right input) and two output clocks (left output and right output) in addition to a PLL mux clock which the SERDES uses for Clock Multiplier Unit (CMU refclock). The PLL mux clock can select from one of the three input clocks. The right output can select between left input and external reference clock while the left output can select between the right input and external reference clock. The driver has support to select PLL mux and left/right output mux as specified in device tree. [rogerq@ti.com: Fix boot lockup caused by accessing a structure member (hw->init) allocated in stack of probe() and accessed in get_parent] [rogerq@ti.com: Fix "Failed to find the parent" warnings] Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: core: Invoke pm_runtime_get_*/pm_runtime_put_* before invoking reset ↵Kishon Vijay Abraham I1-0/+6
callback PHY drivers may try to access PHY registers in the ->reset() callback. Invoke phy_pm_runtime_get_sync() before invoking the ->reset() callback so that the PHY drivers don't have to enable clocks by themselves before accessing PHY registers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: core: Add *release* phy_ops invoked when the consumer relinquishes PHYKishon Vijay Abraham I1-0/+5
Add a new phy_ops *release* invoked when the consumer relinquishes the PHY using phy_put/devm_phy_put. The initializations done by the PHY driver in of_xlate call back can be can be cleaned up here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: phy-meson-gxl-usb2: get optional clock by devm_clk_get_optional()Chunfeng Yun1-8/+3
Use devm_clk_get_optional() to get optional clock Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: socionext: get optional clock by devm_clk_get_optional()Chunfeng Yun2-14/+6
Use devm_clk_get_optional() to get optional clock Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: qcom-qusb2: get optional clock by devm_clk_get_optional()Chunfeng Yun1-8/+3
Use devm_clk_get_optional() to get optional clock Cc: Andy Gross <andy.gross@linaro.org> Cc: David Brown <david.brown@linaro.org> Cc: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: phy-mtk-tphy: get optional clock by devm_clk_get_optional()Chunfeng Yun1-7/+3
Use devm_clk_get_optional() to get optional clock Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: renesas: rcar-gen3-usb2: enable/disable independent irqsYoshihiro Shimoda1-25/+160
Since the previous code enabled/disabled the irqs both OHCI and EHCI, it is possible to cause unexpected interruptions. To avoid this, this patch creates multiple phy instances from phandle and enables/disables independent irqs by the instances. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Tested-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: renesas: rcar-gen3-usb2: Use pdev's device pointer on dev_vdbg()Yoshihiro Shimoda1-4/+6
To implement multiple phy instances in the future, this patch uses pdev's device pointer on dev_vdbg() instead of the phy's device pointer. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: rcar-gen3-usb2: Add support for r8a77470Biju Das2-7/+34
This patch adds support for r8a77470 (RZ/G1C). We can reuse this driver for initializing timing/interrupt generation registers. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: renesas: phy-rcar-gen2: Add support for r8a77470Biju Das1-12/+118
This patch adds support for RZ/G1C (r8a77470) SoC. RZ/G1C SoC has a PLL register shared between hsusb0 and hsusb1. Compared to other RZ/G1 and R-Car Gen2/3, USB Host needs to deassert the pll reset. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-and-Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: ti-pipe3: Fix PCIe power up sequenceRoger Quadros1-6/+6
TRM [1] mentions that we need to power up PCIESS_PHY_TX and PCIESS_PHY_RX before configuring PCIe_PHY_RX SCP settings. See "Table 26-81. PCIePHY Subsystem Low-Level Programming Sequence". [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: ti-pipe3: Fix SATA & USB PHY power up sequenceRoger Quadros1-14/+30
As per "Table 26-7. SATA PHY Subsystem Low-Level Programming Sequence" in TRM [1] we need to turn on SATA_PHY_TX before SATA_PHY_RX. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: ti-pipe3: improve DPLL stability for SATA & USBRoger Quadros1-42/+173
For increased DPLL stability use the settings recommended in the TRM [1] for PHY_RX registers for SATA and USB. For SATA we need to use spread spectrum settings even though we don't have spread spectrum enabled. The suggested non-spread spectrum settings don't work. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: ti-pipe3: Introduce mode property in driver dataRoger Quadros1-36/+57
Introduce a mode property in the driver data so that we don't have to keep using "of_device_is_compatible()" throughtout the driver. No functional change. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: ti-pipe3: fix missing bit-wise or operator when assigning valColin Ian King1-1/+1
There seems to be a missing bit-wise or operator when setting val, fix this by adding it in. Fixes: 2796ceb0c18a ("phy: ti-pipe3: Update pcie phy settings") Cc: stable@vger.kernel.org # v4.19+ Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: mediatek: Add UFS M-PHY driverStanley Chu3-0/+256
Add UFS M-PHY driver on MediaTek chipsets. Signed-off-by: Stanley Chu <stanley.chu@mediatek.com> Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: rockchip-emmc: Allow to set drive impedance via DTS.Christoph Muellner1-2/+28
The rockchip-emmc PHY can be configured with different drive impedance values. Currenlty a value of 50 Ohm is hard coded into the driver. This patch introduces the DTS property 'drive-impedance-ohm' for the rockchip-emmc phy node, which uses the value from the DTS to setup the drive impedance accordingly. Signed-off-by: Christoph Muellner <christoph.muellner@theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: ufs-qcom: Refactor all init steps into phy_poweronEvan Green5-144/+46
The phy code was using implicit sequencing between the PHY driver and the UFS driver to implement certain hardware requirements. Specifically, the PHY reset register in the UFS controller needs to be deasserted before serdes start occurs in the PHY. Before this change, the code was doing this by utilizing the two phy callbacks, phy_init() and phy_poweron(), as "init step 1" and "init step 2", where the UFS driver would deassert reset between these two steps. This makes it challenging to power off the regulators in suspend, as regulators are initialized in init, not in poweron(), but only poweroff() is called during suspend, not exit(). For UFS, move the actual firing up of the PHY to phy_poweron() and phy_poweroff() callbacks, rather than init()/exit(). UFS calls phy_poweroff() during suspend, so now all clocks and regulators for the phy can be powered down during suspend. QMP is a little tricky because the PHY is also shared with PCIe and USB3, which have their own definitions for init() and poweron(). Rename the meaty functions to _enable() and _disable() to disentangle from the PHY core names, and then create two different ops structures: one for UFS and one for the other PHY types. In phy-qcom-ufs, remove the 'is_powered_on' and 'is_started' guards, as the generic PHY code does the reference counting. The 14/20nm-specific init functions get collapsed into the generic power_on() function, with the addition of a calibrate() callback specific to 14/20nm. Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: qcom: Utilize UFS reset controllerEvan Green5-0/+76
Move the PHY reset from ufs-qcom into the respective PHYs. This will allow us to merge the two phases of UFS PHY initialization. Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: amlogic: Add Amlogic G12A USB3 + PCIE Combo PHY DriverNeil Armstrong3-0/+425
This adds support for the shared USB3 + PCIE PHY found in the Amlogic G12A SoC Family. It supports USB3 Host mode or PCIE 2.0 mode, depending on the layout of the board. Selection is done by the #phy-cells, making the mode static and exclusive. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: amlogic: add Amlogic G12A USB2 PHY DriverNeil Armstrong3-0/+353
This adds support for the USB2 PHY found in the Amlogic G12A SoC Family. It supports Host and/or Peripheral mode, depending on it's position. The first PHY is only used as Host, but the second supports Dual modes defined by the USB Control Glue HW in front of the USB Controllers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: sr-usb: Add Stingray USB PHY driverSrinath Mannam3-0/+406
USB PHY driver supports two types of stingray USB PHYs - Type 1 is a combo PHY contains two PHYs, one SS and one HS. - Type 2 is a single HS PHY. These two PHY versons support both Generic xHCI host controller driver and BDC Broadcom device controller driver. Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: tegra: xusb: Add Tegra186 supportJC Kuo4-0/+933
Add support for the XUSB pad controller found on Tegra186 SoCs. It is mostly similar to the same IP found on earlier chips, but the number of pads exposed differs, as do the programming sequences. Note that the DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_PLL power supplies of the XUSB pad controller require strict power sequencing and are therefore controlled by the PMIC on Tegra186. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> [dan.carpenter@oracle.com: Fix testing the wrong variable in probe()] Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> [yuehaibing@huawei.com: Make two functions static to fix sparse warning] Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: tegra: xusb: Add support for power suppliesThierry Reding2-1/+38
Support enabling various supplies needed to provide power to the PLLs and logic used to drive the USB, PCI and SATA pads. Reviewed-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: tegra: xusb: Parse dual-role mode propertyThierry Reding2-0/+24
The device tree bindings document the "mode" property of "ports" subnodes, but the driver was not parsing the property. In preparation for adding role switching, parse the property at probe time. Based on work by JC Kuo <jckuo@nvidia.com>. Reviewed-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: tegra: xusb: Skip single function lane programmingJC Kuo1-1/+5
Tegra186 USB2 pads and USB3 pads do not have hardware mux for changing the pad function. For such "lanes", we can skip the lane mux register programming. Signed-off-by: JC Kuo <jckuo@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: sun4i-usb: Make sure to disable PHY0 passby for peripheral modePaul Kocialkowski1-0/+4
On platforms where the MUSB and HCI controllers share PHY0, PHY passby is required when using the HCI controller with the PHY, but it must be disabled when the MUSB controller is used instead. Without this, PHY0 passby is always enabled, which results in broken peripheral mode on such platforms (e.g. H3/H5). Fixes: ba4bdc9e1dc0 ("PHY: sunxi: Add driver for sunxi usb phy") Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: fix platform_no_drv_owner.cocci warningsYueHaibing1-1/+0
Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: mapphone-mdm6600: add gpiolib dependencyArnd Bergmann1-1/+1
gcc points out that when CONFIG_GPIOLIB is disabled, gpiod_get_array_value_cansleep() returns 0 but fails to set its output: drivers/phy/motorola/phy-mapphone-mdm6600.c: In function 'phy_mdm6600_status': drivers/phy/motorola/phy-mapphone-mdm6600.c:220:24: error: 'values[0]' is used uninitialized in this function [-Werror=uninitialized] This could be fixed more generally in gpiolib by returning a failure code, but for this specific case, the easier workaround is to add a gpiolib dependency. Fixes: 5d1ebbda0318 ("phy: mapphone-mdm6600: Add USB PHY driver for MDM6600 on Droid 4") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: ti: usb2: fix OMAP_CONTROL_PHY dependencyArnd Bergmann1-1/+1
With randconfig build testing on arm64, we can run into a configuration that has CONFIG_OMAP_CONTROL_PHY=m and CONFIG_OMAP_USB2=y, which in turn causes a link failure: drivers/phy/ti/phy-omap-usb2.o: In function `omap_usb_phy_power': phy-omap-usb2.c:(.text+0x17c): undefined reference to `omap_control_phy_power' I could not come up with a good way to correctly describe the relation of the two symbols, but if we just select CONFIG_OMAP_CONTROL_PHY during compile testing, we can no longer run into the broken configuration. Fixes: 6777cee3a872 ("phy: ti: usb2: Add support for AM654 USB2 PHY") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: allwinner: allow compile testingArnd Bergmann1-3/+6
Some allwinner specific drivers can be built for testing purposes on non-sunxi configurations, which then results in a harmless warning: WARNING: unmet direct dependencies detected for PHY_SUN6I_MIPI_DPHY Depends on [n]: ARCH_SUNXI [=n] && HAS_IOMEM [=y] && OF [=y] && RESET_CONTROLLER [=y] Selected by [y]: - DRM_SUN6I_DSI [=y] && HAS_IOMEM [=y] && DRM_SUN4I [=y] Allow compile-test here as well to avoid the warning, and improve overall build coverage. Fixes: 5d134abf9530 ("phy: Move Allwinner A31 D-PHY driver to drivers/phy/") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: qcom-ufs: Make ufs_qcom_phy_disable_iface_clk staticYueHaibing1-1/+1
Fix sparse warning: drivers/phy/qualcomm/phy-qcom-ufs.c:462:6: warning: symbol 'ufs_qcom_phy_disable_iface_clk' was not declared. Should it be static? Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: rockchip-typec: Make usb3_pll_cfg and dp_pll_cfg staticYueHaibing1-2/+2
Fix sparse warning: drivers/phy/rockchip/phy-rockchip-typec.c:403:16: warning: symbol 'usb3_pll_cfg' was not declared. Should it be static? drivers/phy/rockchip/phy-rockchip-typec.c:420:16: warning: symbol 'dp_pll_cfg' was not declared. Should it be static? Signed-off-by: YueHaibing <yuehaibing@huawei.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-04-17phy: phy-twl4030-usb: Fix cable state handlingTony Lindgren1-22/+13
With the recent regulator changes I noticed new warnings on doing rmmod of phy-twl4030-usb: WARNING: CPU: 0 PID: 1080 at drivers/regulator/core.c:2046 _regulator_put ... Turns out we can currently miss disconnect at least for cases where status is 0 and linkstat is 0. And in that case doing rmmod phy-twl4030-usb will produce the regulator_put() warning. This is because the missed disconnect causes unbalanced PM runtime calls and the regulators will be on exit. Let's fix the issue by using an atomic flag for the cable state to make sure that PM runtime won't get out of sync with the cable state. That way we can also simplify the code a bit. Note that we can also drop the old comments, those relate to issues that the battery charger driver and musb driver is dealing with rather than the USB PHY driver. Cc: NeilBrown <neilb@suse.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2019-03-26phy: sun4i-usb: Support set_mode to USB_HOST for non-OTG PHYsChen-Yu Tsai1-1/+4
While only the first PHY supports mode switching, the remaining PHYs work in USB host mode. They should support set_mode with mode=USB_HOST instead of failing. This is especially needed now that the USB core does set_mode for all USB ports, which was added in commit b97a31348379 ("usb: core: comply to PHY framework"). Make set_mode with mode=USB_HOST a no-op instead of failing for the non-OTG USB PHYs. Fixes: 6ba43c291961 ("phy-sun4i-usb: Add support for phy_set_mode") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Cc: stable <stable@vger.kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-03-08Merge tag 'drm-next-2019-03-06' of git://anongit.freedesktop.org/drm/drmLinus Torvalds3-0/+331
Pull drm updates from Dave Airlie: "This is the main drm pull request for the 5.1 merge window. The big changes I'd highlight are: - nouveau has HMM support now, there is finally an in-tree user so we can quieten down the rip it out people. - i915 now enables fastboot by default on Skylake+ - Displayport Multistream support has been refactored and should hopefully be more reliable. Core: - header cleanups aiming towards removing drmP.h - dma-buf fence seqnos to 64-bits - common helper for DP mst hotplug for radeon,i915,amdgpu + new refcounting scheme - MST i2c improvements - drm_syncobj_cb removal - ARM FB compression fourcc - P010 + P016 fourcc - allwinner tiled format modifier - i2c over aux I2C_M_STOP support - DRM_AUTH handling fixes TTM: - ref/unref renaming New driver: - ARM komeda display driver scheduler: - refactor mirror list handling - rework hw fence processing - 0 run queue entity fix bridge: - TI DS90C185 LVDS bridge - thc631lvdm83d bridge improvements - cadence + allwinner DSI ported to generic phy panels: - Sitronix ST7701 panel - Kingdisplay KD097D04 - LeMaker BL035-RGB-002 - PDA 91-00156-A0 - Innolux EE101IA-01D i915: - Enable fastboot by default on SKL+/VLV/CHV - Export RPCS configuration for ICL media driver - Coffelake PCI ID - CNL clocks setup fixes - ACPI/PMIC support for MIPI/DSI - Per-engine WA init for all engines - Shrinker locking fixes - Kerneldoc updates - Lots of ring improvements and reset fixes - Coffeelake GVT Support - VFIO GVT EDID Region support - runtime PM wakeref tracking - ILK->IVB primary plane enable delays - userptr mutex locking fixes - DSI fixes - LVDS/TV cleanups - HW readout fixes - LUT robustness fixes - ICL display and watermark fixes - gem mmap race fix amdgpu: - add scheduled dependencies interface - DCC on scanout surfaces - vega10/20 BACO support - Multiple IH rings on soc15 - XGMI locking fixes - DC i2c/aux cleanups - runtime SMU debug interface - Kexec improvmeents - SR-IOV fixes - DC freesync + ABM fixes - GDS fixes - GPUVM fixes - vega20 PCIE DPM switching fixes - Context priority handling fixes radeon: - fix missing break in evergreen parser nouveau: - SVM support via HMM msm: - QCOM Compressed modifier support exynos: - s5pv210 rotator support imx: - zpos property support - pending update fixes v3d: - cache flush improvments vc4: - reflection support - HDMI overscan support tegra: - CEC refactoring - HDMI audio fixes - Tegra186 prep work - SOR crossbar device tree fixes sun4i: - implicit fencing support - YUV and scalar support improvements - A23 support - tiling fixes atmel-hlcdc: - clipping and rotation property fixes qxl: - BO and PRIME improvements - generic fbdev emulation dw-hdmi: - HDMI 2.0 2160p - YUV420 ouput rockchip: - implicit fencing support - reflection proerties virtio-gpu: - use generic fbdev emulation tilcdc: - cpufreq vs crtc init fix rcar-du: - R8A774C0 support - D3/E3 RGB output routing fixes and DPAD0 support - RA87744 LVDS support bochs: - atomic and generic fbdev emulation - ID mismatch error on bochs load meson: - remove firmware fbs" * tag 'drm-next-2019-03-06' of git://anongit.freedesktop.org/drm/drm: (1130 commits) drm/amd/display: Use vrr friendly pageflip throttling in DC. drm/imx: only send commit done event when all state has been applied drm/imx: allow building under COMPILE_TEST drm/imx: imx-tve: depend on COMMON_CLK drm/imx: ipuv3-plane: add zpos property drm/imx: ipuv3-plane: add function to query atomic update status gpu: ipu-v3: prg: add function to get channel configure status gpu: ipu-v3: pre: add double buffer status readback drm/amdgpu: Bump amdgpu version for context priority override. drm/amdgpu/powerplay: fix typo in BACO header guards drm/amdgpu/powerplay: fix return codes in BACO code drm/amdgpu: add missing license on baco files drm/bochs: Fix the ID mismatch error drm/nouveau/dmem: use dma addresses during migration copies drm/nouveau/dmem: use physical vram addresses during migration copies drm/nouveau/dmem: extend copy function to allow direct use of physical addresses drm/nouveau/svm: new ioctl to migrate process memory to GPU memory drm/nouveau/dmem: device memory helpers for SVM drm/nouveau/svm: initial support for shared virtual memory drm/nouveau: prepare for enabling svm with existing userspace interfaces ...
2019-03-06Merge tag 'usb-5.1-rc1' of ↵Linus Torvalds21-130/+1309
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB/PHY updates from Greg KH: "Here is the big USB/PHY driver pull request for 5.1-rc1. The usual set of gadget driver updates, phy driver updates, xhci updates, and typec additions. Also included in here are a lot of small cleanups and fixes and driver updates where needed. All of these have been in linux-next for a while with no reported issues" * tag 'usb-5.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (167 commits) wusb: Remove unnecessary static function ckhdid_printf usb: core: make default autosuspend delay configurable usb: core: Fix typo in description of "authorized_default" usb: chipidea: Refactor USB PHY selection and keep a single PHY usb: chipidea: Grab the (legacy) USB PHY by phandle first usb: chipidea: imx: set power polarity dt-bindings: usb: ci-hdrc-usb2: add property power-active-high usb: chipidea: imx: remove unused header files usb: chipidea: tegra: Fix missed ci_hdrc_remove_device() usb: core: add option of only authorizing internal devices usb: typec: tps6598x: handle block writes separately with plain-I2C adapters usb: xhci: Fix for Enabling USB ROLE SWITCH QUIRK on INTEL_SUNRISEPOINT_LP_XHCI usb: xhci: fix build warning - missing prototype usb: xhci: dbc: Fixing typo error. usb: xhci: remove unused member 'parent' in xhci_regset struct xhci: tegra: Prevent error pointer dereference USB: serial: option: add Telit ME910 ECM composition usb: core: Replace hardcoded check with inline function from usb.h usb: core: skip interfaces disabled in devicetree usb: typec: mux: remove redundant check on variable match ...
2019-02-18Merge v5.0-rc7 into drm-nextDave Airlie4-6/+8
Backmerging for nouveau and imx that needed some fixes for next pulls. Signed-off-by: Dave Airlie <airlied@redhat.com>
2019-02-12Merge tag 'phy-for-5.1' of ↵Greg Kroah-Hartman21-130/+1309
git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next Kishon writes: phy: for 5.1 *) Add a new driver to support Armada 3700 COMPHY IP (supports SATA, USB3, PCIe) *) Add a new driver to support Armada UTMI PHY *) Add a new driver to support Cadence D-PHY *) Extend omap-usb2 PHY driver to be used for AM654 USB2 PHY *) Extend qcom-qmp PHY driver to be used for UFS PHY and USB3 PHY in Qualcomm MSM8998 *) Extend qcom-qusb2 PHY driver to support QUSB2 PHY in Qualcomm MSM8998 *) Remove module specific code that is present for drivers that can be only built-in *) Allow Freescale IMX8MQ USB to be used for multiple SoCs and not just i.MX8MQ *) Cleanups such as switch to SPDX identifier, use readl_poll_timeout macro, remove unused headers etc., Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> * tag 'phy-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: (32 commits) phy: qcom-qmp: Add QMP UFS PHY support for msm8998 dt-bindings: phy-qcom-qmp: Add qcom,msm8998-qmp-ufs-phy phy: bcm-sr-pcie: Change operation when PIPEMUX=1 phy: Add Cadence D-PHY support dt-bindings: phy: Move the Cadence D-PHY bindings phy: dphy: Clarify lanes parameter documentation phy: dphy: Change units of wakeup and init parameters phy: dphy: Remove unused header MAINTAINERS: phy: fill Armada 3700 PHY drivers entry dt-bindings: phy: mvebu-utmi: add UTMI PHY bindings phy: add A3700 UTMI PHY driver MAINTAINERS: phy: add entry for Armada 3700 COMPHY driver dt-bindings: phy: mvebu-comphy: extend the file to describe a3700 bindings phy: add A3700 COMPHY support phy: mvebu-cp110-comphy: fix port check in ->xlate() phy: armada375-usb2: switch to SPDX license identifier phy: make phy-armada375-usb2 explicitly non-modular phy: make phy-mvebu-sata explicitly non-modular phy: make phy-core explicitly non-modular phy: qcom-qusb2: Add QUSB2 PHY support for msm8998 ...
2019-02-12phy: qcom-qmp: Add QMP UFS PHY support for msm8998Marc Gonzalez1-0/+3
Use same init sequence as sdm845. Reviewed-by: Jeffrey Hugo <jhugo@codeaurora.org> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 08:02:29 +0000