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2017-07-27phy: bcm-ns-usb3: fix MDIO_BUS dependencyArnd Bergmann1-1/+1
The driver attempts to 'select MDIO_DEVICE', but the code is actually a loadable module when PHYLIB=m: drivers/phy/broadcom/phy-bcm-ns-usb3.o: In function `bcm_ns_usb3_mdiodev_phy_write': phy-bcm-ns-usb3.c:(.text.bcm_ns_usb3_mdiodev_phy_write+0x28): undefined reference to `mdiobus_write' drivers/phy/broadcom/phy-bcm-ns-usb3.o: In function `bcm_ns_usb3_module_exit': phy-bcm-ns-usb3.c:(.exit.text+0x18): undefined reference to `mdio_driver_unregister' drivers/phy/broadcom/phy-bcm-ns-usb3.o: In function `bcm_ns_usb3_module_init': phy-bcm-ns-usb3.c:(.init.text+0x18): undefined reference to `mdio_driver_register' phy-bcm-ns-usb3.c:(.init.text+0x38): undefined reference to `mdio_driver_unregister' Using 'depends on MDIO_BUS' instead will avoid the link error. Fixes: af850e14a7ae ("phy: bcm-ns-usb3: add MDIO driver using proper bus layer") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-06-16phy: bcm-ns-usb3: add MDIO driver using proper bus layerRafał Miłecki2-1/+105
As USB 3.0 PHY is attached to the MDIO bus this module should provide a MDIO driver and use a proper bus layer. This is a proper (cleaner) solution which doesn't require code to know this specific MDIO bus details. It also allows reusing the driver with other MDIO buses. For now keep platform device support in place. We may consider dropping it once MDIO bindings gets used "everywhere". Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-16phy: bcm-ns-usb3: enable MDIO in the platform specific codeRafał Miłecki1-12/+6
When we finally start using MDIO layer then bus initialization will be handled in a separated driver. It means our code handling this has to be used for the platform driver only. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-16phy: bcm-ns-usb3: use pointer for PHY writing functionRafał Miłecki1-42/+56
Our current writing function accesses PHY directly bypassing MDIO layer. The aim is to extend this module to also behave as MDIO driver. This will require using different writing function which can be handled cleanly by having an extra pointer like this. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-16phy: bcm-ns-usb3: always wait for idle after writing to the PHY regRafał Miłecki1-10/+1
Move MDIO specific code to the writing helper function. This makes init code a bit more generic and doesn't require it to track what happens after every write. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-16phy: Add stingray SATA phy supportSrinath Mannam1-0/+73
This patch adds support for stingray SATA phy in the SATA BRCM phy driver. Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-16phy: cpcap-usb: Fix missing return statementTony Lindgren1-0/+2
Commit 8ae904e3c236 ("phy: cpcap-usb: Add CPCAP PMIC USB support") is missing return statement as noted by Colin Ian King <colin.king@canonical.com>. If the optional pins are not configured, we just want to return early and not attempt to configure the pins. Fixes: 8ae904e3c236 ("phy: cpcap-usb: Add CPCAP PMIC USB support") Reported-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-09phy: phy-bcm-ns2-usbdrd: Broadcom USB DRD PHY driver for Northstar2Raviteja Garimella3-0/+451
This is driver for USB DRD PHY used in Broadcom's Northstar2 SoC. The phy can be configured to be in Device mode or Host mode based on the type of cable connected to the port. The driver registers to extcon framework to get appropriate connect events for Host/Device cables connect/disconnect states based on VBUS and ID interrupts. Signed-off-by: Raviteja Garimella <raviteja.garimella@broadcom.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-09phy: cpcap-usb: add MUSB dependencyArnd Bergmann1-0/+1
When MUSB is a loadable module, we get a link error for a built-in CPCAP driver: drivers/phy/built-in.o: In function `cpcap_usb_phy_remove': phy-cpcap-usb.c:(.text+0xed9): undefined reference to `musb_mailbox' This adds a Kconfig dependency to prevent this broken configuration, enforcing that CPCAP can only be a module when MUSB is also a module. Fixes: 68a1f7c9d470 ("phy: cpcap-usb: Add CPCAP PMIC USB support") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-09phy: tusb1210: implement ->set_mode()Felipe Balbi1-0/+35
->set_mode() can be used to tell PHY to prepare itself to enter USB Host/Peripheral mode and that's very important for DRD configurations. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-09phy: tusb1210: add support for TUSB1211Felipe Balbi1-1/+2
TUSB1211 is software compatible with TUSB1210 and as such we don't need an entire new driver to control it. Let's add its product ID to the existing TUSB1210 driver instead. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-07phy: rcar-gen3-usb3: add support for R-Car Gen3 USB 3.0 PHYYoshihiro Shimoda3-0/+234
The USB 3.0 PHY modules of R-Car Gen3 SoCs have: - Spread spectrum clock (ssc). - Using USB 2.0 EXTAL clock instead of USB 3.0 clock. - Enabling VBUS detection for usb3.0 peripheral. So, this driver supports these features. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-06phy: rockchip-inno-usb2: add support of usb2-phy for rk3228 SoCsFrank Wang1-0/+60
This adds support usb2-phy for rk3228 SoCs and amend phy Documentation. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-06phy: rockchip-inno-usb2: add one phy comprises with two host-ports supportWilliam Wu1-3/+6
At the current rockchip-inno-usb2 phy driver framework, it can only support usb2-phy which comprises with one otg-port and one host-port. However, some Rockchip SoCs' (e.g RK3228, RK3229) usb2-phy comprises with two host-ports, so we use index of otg id for one host-port configuration, and make it work the same as otg-port host mode. Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-06phy: rockchip-inno-usb2: increase otg sm work first schedule timeWilliam Wu1-1/+1
In rockchip-inno-usb2 phy driver, we use otg_sm_work to dynamically manage power consumption for phy otg-port. If the otg-port works as peripheral mode and does not communicate with usb host, we will suspend phy. But once suspend phy, the phy no longer has any internal clock running, include the utmi_clk which supplied for usb controller. So if we suspend phy before usb controller init, it will cause usb controller fail to initialize. Specifically, without this patch, the observed order is: 1. unplug usb cable 2. start system, do dwc2 controller probe 3. dwc2_lowlevel_hw_enable() - phy_init() - rockchip_usb2phy_init() - schedule otg_sm_work after 2s put phy in suspend, and close utmi_clk 4. dwc2_hsotg_udc_start() - fail to initialize the usb core Generally, dwc2_hsotg_udc_start() can be called within 5s after start system on Rockchip platform, so we increase the the first schedule delay time to 6s for otg_sm_work afer usb controller calls phy_init(), this can make sure that the usb controller completes initialization before phy enter suspend. Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-06phy: rockchip-inno-usb2: add a delay after phy resumeWilliam Wu1-0/+3
When resume phy, it need about 1.5 ~ 2ms to wait for utmi_clk which used for USB controller to become stable. Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-06phy: cpcap-usb: Add CPCAP PMIC USB supportTony Lindgren5-0/+692
Some Motorola phones like droid 4 use a custom CPCAP PMIC that has a multiplexing USB PHY. This USB PHY can operate at least in four modes using pin multiplexing and two control GPIOS: - Pass through companion PHY for the SoC USB PHY - ULPI PHY for the SoC - Pass through USB for the modem - UART debug console for the SoC This patch adds support for droid 4 USB PHY and debug UART modes, support for other modes can be added later on as needed. Both peripheral and host mode are working for the USB. The host mode depends on the cpcap-charger driver for VBUS. VBUS and ID pin detection are done using cpcap-adc IIO ADC driver. Cc: devicetree@vger.kernel.org Cc: Marcel Partap <mpartap@gmx.net> Cc: Michael Scott <michael.scott@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Tested-by: Sebastian Reichel <sre@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-06phy: meson8b-usb2: add support for the USB PHY on Meson8 SoCsMartin Blumenstingl2-5/+6
Meson8 uses the same USB PHY as found on the Meson8b and GXBB SoCs. Add a new of_device_id to indicate this. Also update the Kconfig option and MODULE_DESCRIPTION accordingly. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-06phy: meson: add USB2 PHY support for Meson GXL and GXMMartin Blumenstingl3-0/+287
This adds a new driver for the USB2 PHYs found on Meson GXL and GXM SoCs (both SoCs are using the same USB PHY register layout). The USB2 PHY is a simple PHY which only has a few registers to configure the mode (host/device) and a reset register (to enable/disable the PHY). Unfortunately there are no datasheets available for this PHY. The driver was written by reading the code from Amlogic's GPL kernel sources and by analyzing the registers on an actual GXL and GXM device running the kernel that was shipped on the boards I have. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-01phy: Group vendor specific phy driversVivek Gautam83-537/+582
Adding vendor specific directories in phy to group phy drivers under their respective vendor umbrella. Also updated the MAINTAINERS file to reflect the correct directory structure for phy drivers. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: David S. Miller <davem@davemloft.net> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: Guenter Roeck <linux@roeck-us.net> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Stephen Boyd <stephen.boyd@linaro.org> Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-omap@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-usb@vger.kernel.org Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-01phy: Move ULPI phy header out of drivers to include pathVivek Gautam2-33/+1
Although ULPI phy is currently being used by tusb1210, there can be other consumers too in future. So move this to the includes path for phy. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Cc: Stephen Boyd <stephen.boyd@linaro.org> Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-omap@vger.kernel.org Cc: linux-usb@vger.kernel.org Acked-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-01phy: qcom-usb: Remove unused ulpi phy headerVivek Gautam2-4/+2
Ulpi phy header is not used for anything. Remove the same from qcom-hs and qcom-hsic phy drivers. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Suggested-by: Stephen Boyd <stephen.boyd@linaro.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-usb@vger.kernel.org Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-06-01phy: qualcomm: phy-qcom-qmp: fix application of sizeof to pointerFengguang Wu1-1/+1
drivers/phy/qualcomm/phy-qcom-qmp.c:847:37-43: ERROR: application of sizeof to pointer sizeof when applied to a pointer typed expression gives the size of the pointer Generated by: scripts/coccinelle/misc/noderef.cocci CC: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-05-19phy: qcom-qmp: fix return value check in qcom_qmp_phy_create()Wei Yongjun1-6/+6
In case of error, the function of_iomap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: qcom-qusb2: add NVMEM dependencyTobias Regnery1-0/+1
With CONFIG_NVMEM=m and CONFIG_PHY_QCOM_QUSB2=y we get a link error from calls to devm_nvmem_cell_get and nvmem_cell_read: drivers/built-in.o: In function `qusb2_phy_probe': binder.c:(.text+0x4750): undefined reference to `devm_nvmem_cell_get' drivers/built-in.o: In function `qusb2_phy_init': binder.c:(.text+0x489c): undefined reference to `nvmem_cell_read' Fix this by adding a Kconfig dependency to ensure we can only have this driver built in when the nvmem functions are also built in or we see the empty stub functions. We can still build this driver as a module when the nvmem core is build as module, too. Fixes: deffad633413 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips") Signed-off-by: Tobias Regnery <tobias.regnery@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: rockchip-usb: Add vbus regulator support.Sjoerd Simons1-0/+19
On rockchip devices vbus is supplied by a separate power supply, often through a regulator. Add support for describing the the regulator in device-tree following the same convention as several other usb phy's. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: bcm-ns-usb3: split all writes into reg & val pairsRafał Miłecki1-20/+49
So far all the PHY initialization was implemented using some totally magic values. There was some pattern there but it wasn't clear what is it about. Thanks to the patch submitted by Broadcom: [PATCH 5/6] phy: Add USB3 PHY support for Broadcom NSP SoC and the upstream "iproc-mdio" driver we now know there is a MDIO bus underneath with PHY(s) and their registers. It allows us to clean the driver a bit by making all these values less magical. The next step is switching to using a proper MDIO layer. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Jon Mason <jon.mason@broadcom.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: qcom-qmp: new qmp phy driver for qcom-chipsetsVivek Gautam3-0/+1162
Qualcomm SOCs have QMP phy controller that provides support to a number of controller, viz. PCIe, UFS, and USB. Add a new driver, based on generic phy framework, for this phy controller. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chipsVivek Gautam3-0/+504
PHY transceiver driver for QUSB2 phy controller that provides HighSpeed functionality for DWC3 controller present on Qualcomm chipsets. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: rockchip-inno-usb2: add support of usb2-phy for rk3328Meng Dongyang1-0/+44
Add usb2-phy config information in the data of match table for rk3328. Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: phy-mt65xx-usb3: disable 100uA extraction from SS port to HS portChunfeng Yun1-14/+10
There will be a problem if SS port is diasbled and HS port extracts 100uA from SS port, so disable extract 100uA from SS port in the case, when disable it, PA0_RG_USB20_INTR_EN should be set, otherwise HS port only works on LS. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: phy-mt65xx-usb3: add support for new version phyChunfeng Yun1-128/+218
There are some variations from mt2701 to mt2712: 1. banks shared by multiple ports are put back into each port, such as SPLLC and U2FREQ; 2. add a new bank MISC for u2port, and CHIP for u3port; 3. bank's offset in each port are also rearranged; Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: phy-mt65xx-usb3: move clock from phy node into port nodesChunfeng Yun1-2/+25
each port has its own reference clock, the HighSpeed port is 48M, and the SuperSpeed port is usually 26M, put them into port node for flexibility, this can close clock if the port is not used. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: phy-mt65xx-usb3: split SuperSpeed port into two onesChunfeng Yun1-74/+75
Currently usb3 port in fact includes two sub-ports, but it is not flexible for some cases, such as following one: usb3 port0 includes u2port0 and u3port0; usb2 port0 includes u2port1; If wants to support only HS, we can use u2port0 or u2port1, when select u2port0, u3port0 is not needed; If wants to support SS, we can compound u2port0 and u3port0, or u2port1 and u3port0, if select latter one, u2port0 is not needed. So it's more flexible to split usb3 port into two ones and also try best to save power by disabling unnecessary ports. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: phy-mt65xx-usb3: increase LFPS filter thresholdChunfeng Yun1-0/+9
Increase LFPS filter threshold to avoid some fake remote wakeup signal which cause U3 link fail and link to U2 only at about 0.01% probability. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: phy-mt65xx-usb3: improve RX detection stable timeChunfeng Yun1-0/+18
The default value of RX detection stable time is 10us, and this margin is too big for some critical cases which cause U3 link fail and link to U2(probability is about 1%). So change it to 5us. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: sun4i-usb: enable PHY0 dual route switching for A64 USB PHYIcenowy Zheng1-0/+1
Allwinner A64 SoC features a switchable PHY0 like the one in H3, which can switch between a MUSB controller and a pair of OHCI/EHCI controller. Enable PHY0 route auto switching for A64. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: rcar-gen3-usb2: fix implementation for runtime PMYoshihiro Shimoda1-7/+24
This patch fixes an issue that this driver doesn't take care of the runtime PM. This code assumed that devm_phy_create() called pm_runtime_enable(dev), but it misunderstood the dev_phy_create()'s specification. This driver should call its own pm_runtime_enable() before dev_phy_create(). Fixes: f3b5a8d9b50d ("phy: rcar-gen3-usb2: Add R-Car Gen3 USB2 PHY driver") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: rockchip-inno-usb2: fix spelling mistake: "connecetd" -> "connected"Colin Ian King1-6/+3
trivial fix to spelling mistake in dev_dbg message, also rejoin lines to clean up checkpatch warning Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: exynos: Use one define for enable bitKrzysztof Kozlowski3-26/+23
There is no need for separate defines for Exynos4 and Exynos5 phy enable bit and MIPI phy reset bits. In both cases there are the same so simplify it. This reduces number of defines and allows removal of one header file. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: exynos-mipi-video: Use consistent method to address phy registersKrzysztof Kozlowski1-10/+10
Exynos4 MIPI phy registers are defined with macro calculating the offset for given phyN. Use the same method for Exynos5420 to be consistent. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: exynos5: Remove duplicated defines of PHY register definesKrzysztof Kozlowski2-0/+2
Phy drivers access PMU region through regmap provided by exynos-pmu driver. However there is no need to duplicate defines for PMU registers. Instead just use whatever is defined in exynos-regs-pmu.h. This reduces number of defines. Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: exynos4: Remove duplicated defines of PHY register definesKrzysztof Kozlowski1-6/+6
Phy drivers access PMU region through regmap provided by exynos-pmu driver. However there is no need to duplicate defines for PMU registers. Instead just use whatever is defined in exynos-regs-pmu.h. Additionally MIPI PHY registers for Exynos5433 start from the same address as Exynos4 and Exynos5250 so re-use existing defines. This reduces number of defines and allows removal of one header file. Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: meson8b-usb2: fix offsets for some of the registersMartin Blumenstingl1-3/+3
The register offsets for REG_DBG_UART (and all following) were off by 0x4. This was not a problem yet because these registers are currently not used by the driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: sun4i-usb: support automatically switch PHY0 route to MUSB/HCIIcenowy Zheng1-17/+33
On newer Allwinner SoCs (H3 and after), the PHY0 node is routed to both MUSB controller for peripheral and host support (the host support is slightly broken), and a pair of EHCI/OHCI controllers, which provide a better support for host mode. Add support for automatically switch the route of PHY0 according to the status of dr_mode and id det pin. Only H3 have this function enabled in this patch, as further SoCs will be tested later and then have it enabled. As H5 is reusing the PHY driver of H3, this function is also enabled. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: sun4i-usb: add PHYCTL offset for H3 SoCIcenowy Zheng1-0/+1
The config structure of H3 in phy-sun4i-usb driver have the PHYCTL register offset missing. Add it. From the BSP source code, we know that the offset should be 0x10. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: sun4i-usb: change PHYCTL register clearing codeIcenowy Zheng1-4/+2
It seems that all SoCs with the PHYCTL register offset as 0x10 need the PHYCTL register to be cleared before it's written. Change PHYCTL register clearing code to judge whether clearing is needed based on the PHYCTL offset. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-04-10phy: phy-exynos-pcie: make it explicitly non-modularPaul Gortmaker1-6/+2
The Kconfig currently controlling compilation of this code is: drivers/phy/Kconfig:config PHY_EXYNOS_PCIE drivers/phy/Kconfig: bool "Exynos PCIe PHY driver" ...meaning that it currently is not being built as a module by anyone. Lets remove the couple traces of modular infrastructure use, so that when reading the driver there is no doubt it is builtin-only. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Pankaj Dubey <pankaj.dubey@samsung.com> Cc: Vivek Gautam <vivek.gautam@codeaurora.org> Cc: Javier Martinez Canillas <javier@osg.samsung.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-03-09phy: qcom-usb-hs: Add depends on EXTCONStephen Boyd1-0/+1
We get the following compile errors if EXTCON is enabled as a module but this driver is builtin: drivers/built-in.o: In function `qcom_usb_hs_phy_power_off': phy-qcom-usb-hs.c:(.text+0x1089): undefined reference to `extcon_unregister_notifier' drivers/built-in.o: In function `qcom_usb_hs_phy_probe': phy-qcom-usb-hs.c:(.text+0x11b5): undefined reference to `extcon_get_edev_by_phandle' drivers/built-in.o: In function `qcom_usb_hs_phy_power_on': phy-qcom-usb-hs.c:(.text+0x128e): undefined reference to `extcon_get_state' phy-qcom-usb-hs.c:(.text+0x12a9): undefined reference to `extcon_register_notifier' so let's mark this as needing to follow the modular status of the extcon framework. Fixes: 9994a33865f4 e2427b09ba929c2b9 (phy: Add support for Qualcomm's USB HS phy") Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-03-09phy: phy-exynos-pcie: fix the wrong error returnJaehoon Chung1-2/+2
When it doesn't get the blk_base's resource, it was returned the error about phy_base, not blk_base. This patch is for fixing the wrong error return about blk_base. Fixes: cf0adb8e281b ("phy: phy-exynos-pcie: Add support for Exynos PCIe PHY") Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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