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2021-03-31phy: zynqmp: Handle the clock enable/disable properlyManish Narani1-7/+51
The current driver is not handling the clock enable/disable operations properly. The clocks need to be handled correctly by enabling or disabling at appropriate places. This patch adds code to handle the same. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/1616588325-95602-1-git-send-email-manish.narani@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-02-06phy: zynqmp: Simplify code by using dev_err_probe()Michal Simek1-7/+4
Use already prepared dev_err_probe() introduced by commit a787e5400a1c ("driver core: add device probe log helper"). It simplifies EPROBE_DEFER handling. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/0df30548f721b10475a6cc5659beda102fec3c87.1612444300.git.michal.simek@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-07-01phy: zynqmp: Fix unused-function compiler warningTobias Klauser1-4/+2
Mark xpsgtr_suspend and xpsgtr_resume as __maybe_unused to fix the following compiler warning when building with !CONFIG_PM_SLEEP: drivers/phy/xilinx/phy-zynqmp.c:830:12: warning: ‘xpsgtr_resume’ defined but not used [-Wunused-function] 830 | static int xpsgtr_resume(struct device *dev) | ^~~~~~~~~~~~~ drivers/phy/xilinx/phy-zynqmp.c:819:12: warning: ‘xpsgtr_suspend’ defined but not used [-Wunused-function] 819 | static int xpsgtr_suspend(struct device *dev) | ^~~~~~~~~~~~~~ Also drop the existing #ifdef CONFIG_PM so the functions are always compile-checked regardless of CONFIG_PM and/or CONFIG_PM_SLEEP being set. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Tobias Klauser <tklauser@distanz.ch> Link: https://lore.kernel.org/r/20200701141017.26931-1-tklauser@distanz.ch Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-29phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit TransceiverAnurag Kumar Vulisha3-0/+1011
Xilinx ZynqMP SoCs have a Gigabit Transceiver with four lanes. All the high speed peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This patch adds driver for that ZynqMP GT core. Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20200629120054.29338-3-laurent.pinchart@ideasonboard.com Signed-off-by: Vinod Koul <vkoul@kernel.org>