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2009-06-29intel-iommu: Simplify __intel_alloc_iova()David Woodhouse1-31/+18
There's no need for the separate iommu_alloc_iova() function, and certainly not for it to be global. Remove the underscores while we're at it. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Performance improvement for domain_pfn_mapping()David Woodhouse1-9/+17
As with dma_pte_clear_range(), don't keep flushing a single PTE at a time. And also micro-optimise the setting of PTE values rather than using the helper functions to do all the masking. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Performance improvement for dma_pte_clear_range()David Woodhouse1-16/+15
It's a bit silly to repeatedly call domain_flush_cache() for each PTE individually, as we clear it. Instead, batch them up and flush a whole range at a time. We might as well refrain from recalculating the PTE address from scratch each time round the loop too. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Clean up iommu_domain_identity_map()David Woodhouse1-15/+9
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Remove last use of PHYSICAL_PAGE_MASK, for reserving PCI BARsDavid Woodhouse1-10/+3
This is fairly broken anyway -- it doesn't take hotplug into account. We should probably be checking page_is_ram() instead. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Make iommu_flush_iotlb_psi() take pfn as argumentDavid Woodhouse1-12/+9
Most of its callers are having to shift for themselves anyway, so we might as well do it in iommu_flush_iotlb_psi(). Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Change aligned_size() to aligned_nrpages()David Woodhouse1-9/+12
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Clean up intel_map_sg(), remove domain_page_mapping()David Woodhouse1-35/+19
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Use domain_pfn_mapping() in intel_iommu_map_range()David Woodhouse1-2/+5
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Use domain_pfn_mapping() in __intel_map_single()David Woodhouse1-10/+8
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Introduce domain_pfn_mapping()David Woodhouse1-14/+24
... and use it in the trivial cases; the other callers want individual (and bisectable) attention, since I screwed them up the first time... Make the BUG_ON() happen on too-large virtual address rather than physical address, too. That's the one we care about. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Clean up address handling in domain_page_mapping()David Woodhouse1-9/+7
No more masking and alignment; just use pfns. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Change addr_to_dma_pte() to pfn_to_dma_pte()David Woodhouse1-6/+7
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Clean up intel_iommu_unmap_range()David Woodhouse1-9/+5
Use unaligned address for domain->max_addr. That algorithm isn't ideal anyway -- we should probably just look at the last iova in the tree. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Make dma_pte_free_pagetable() take pfns as argumentDavid Woodhouse1-40/+28
With some cleanup of intel_unmap_page(), intel_unmap_sg() and vm_domain_exit() to no longer play with 64-bit addresses. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Make dma_pte_free_pagetable() use pfnsDavid Woodhouse1-18/+22
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Make dma_pte_clear_range() take pfns as argumentDavid Woodhouse1-13/+19
Noting that this is now an _inclusive_ range. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Make dma_pte_clear_range() use pfnsDavid Woodhouse1-13/+9
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Don't just mask out too-big physical addresses; BUG() insteadDavid Woodhouse1-7/+7
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Make dma_pte_clear_one() take pfn not addressDavid Woodhouse1-3/+3
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Change dma_addr_level_pte() to dma_pfn_level_pte()David Woodhouse1-5/+7
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Change address_level_offset() to pfn_level_offset()David Woodhouse1-4/+4
We're shifting the inputs for now, but that'll change... Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Change dma_set_pte_addr() to dma_set_pte_pfn()David Woodhouse1-4/+24
Add some helpers for converting between VT-d and normal system pfns, since system pages can be larger than VT-d pages. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Clean up identity mapping code, remove CONFIG_DMAR_GFX_WADavid Woodhouse1-75/+32
There's no need for the GFX workaround now we have 'iommu=pt' for the cases where people really care about performance. There's no need to have a special case for just one type of device. This also speeds up the iommu=pt path and reduces memory usage by setting up the si_domain _once_ and then using it for all devices, rather than giving each device its own private page tables. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Create new iommu_domain_identity_map() functionDavid Woodhouse1-26/+36
We'll want to do this to a _domain_ (the si_domain) rather than a PCI device. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-29intel-iommu: Only avoid flushing device IOTLB for domain ID 0 in caching modeYu Zhao1-1/+6
In caching mode, domain ID 0 is reserved for non-present to present mapping flush. Device IOTLB doesn't need to be flushed in this case. Previously we were avoiding the flush for domain zero, even if the IOMMU wasn't in caching mode and domain zero wasn't special. Signed-off-by: Yu Zhao <yu.zhao@intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-26intel-iommu: fix Identity Mapping to be arch independentChris Wright1-14/+5
Drop the e820 scanning and use existing function for finding valid RAM regions to add to 1:1 mapping. Signed-off-by: Chris Wright <chrisw@redhat.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-24Merge branch 'release' of ↵Linus Torvalds2-57/+10
git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6 * 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6: (72 commits) asus-laptop: remove EXPERIMENTAL dependency asus-laptop: use pr_fmt and pr_<level> eeepc-laptop: cpufv updates eeepc-laptop: sync eeepc-laptop with asus_acpi asus_acpi: Deprecate in favor of asus-laptop acpi4asus: update MAINTAINER and KConfig links asus-laptop: platform dev as parent for led and backlight eeepc-laptop: enable camera by default ACPI: Rename ACPI processor device bus ID acerhdf: Acer Aspire One fan control ACPI: video: DMI workaround broken Acer 7720 BIOS enabling display brightness ACPI: run ACPI device hot removal in kacpi_hotplug_wq ACPI: Add the reference count to avoid unloading ACPI video bus twice ACPI: DMI to disable Vista compatibility on some Sony laptops ACPI: fix a deadlock in hotplug case Show the physical device node of backlight class device. ACPI: pdc init related memory leak with physical CPU hotplug ACPI: pci_root: remove unused dev/fn information ACPI: pci_root: simplify list traversals ACPI: pci_root: use driver data rather than list lookup ...
2009-06-24Merge branches 'acerhdf', 'acpi-pci-bind', 'bjorn-pci-root', ↵Len Brown2-57/+10
'bugzilla-12904', 'bugzilla-13121', 'bugzilla-13396', 'bugzilla-13533', 'bugzilla-13612', 'c3_lock', 'hid-cleanups', 'misc-2.6.31', 'pdc-leak-fix', 'pnpacpi', 'power_nocheck', 'thinkpad_acpi', 'video' and 'wmi' into release
2009-06-23Intel-IOMMU, intr-remap: source-id checkingWeidong Han2-3/+119
To support domain-isolation usages, the platform hardware must be capable of uniquely identifying the requestor (source-id) for each interrupt message. Without source-id checking for interrupt remapping , a rouge guest/VM with assigned devices can launch interrupt attacks to bring down anothe guest/VM or the VMM itself. This patch adds source-id checking for interrupt remapping, and then really isolates interrupts for guests/VMs with assigned devices. Because PCI subsystem is not initialized yet when set up IOAPIC entries, use read_pci_config_byte to access PCI config space directly. Signed-off-by: Weidong Han <weidong.han@intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-23Intel-IOMMU, intr-remap: set the whole 128bits of irte when modify/free itWeidong Han1-14/+26
Interrupt remapping table entry is 128bits. Currently, it only sets low 64bits of irte in modify_irte and free_irte. This ignores high 64bits setting of irte, that means source-id setting will be ignored. This patch sets the whole 128bits of irte when modify/free it. Following source-id checking patch depends on this. Signed-off-by: Weidong Han <weidong.han@intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-23IOMMU Identity Mapping Support (drivers/pci/intel_iommu.c)Fenghua Yu1-60/+254
Identity mapping for IOMMU defines a single domain to 1:1 map all PCI devices to all usable memory. This reduces map/unmap overhead in DMA API's and improve IOMMU performance. On 10Gb network cards, Netperf shows no performance degradation compared to non-IOMMU performance. This method may lose some of DMA remapping benefits like isolation. The patch sets up identity mapping for all PCI devices to all usable memory. In the DMA API, there is no overhead to maintain page tables, invalidate iotlb, flush cache etc. 32 bit DMA devices don't use identity mapping domain, in order to access memory beyond 4GiB. When kernel option iommu=pt, pass through is first tried. If pass through succeeds, IOMMU goes to pass through. If pass through is not supported in hw or fail for whatever reason, IOMMU goes to identity mapping. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2009-06-22Merge git://git.infradead.org/~dwmw2/iommu-2.6.31Linus Torvalds5-205/+681
* git://git.infradead.org/~dwmw2/iommu-2.6.31: intel-iommu: Fix one last ia64 build problem in Pass Through Support VT-d: support the device IOTLB VT-d: cleanup iommu_flush_iotlb_psi and flush_unmaps VT-d: add device IOTLB invalidation support VT-d: parse ATSR in DMA Remapping Reporting Structure PCI: handle Virtual Function ATS enabling PCI: support the ATS capability intel-iommu: dmar_set_interrupt return error value intel-iommu: Tidy up iommu->gcmd handling intel-iommu: Fix tiny theoretical race in write-buffer flush. intel-iommu: Clean up handling of "caching mode" vs. IOTLB flushing. intel-iommu: Clean up handling of "caching mode" vs. context flushing. VT-d: fix invalid domain id for KVM context flush Fix !CONFIG_DMAR build failure introduced by Intel IOMMU Pass Through Support Intel IOMMU Pass Through Support Fix up trivial conflicts in drivers/pci/{intel-iommu.c,intr_remapping.c}
2009-06-22Merge branch 'linux-next' of ↵Linus Torvalds40-2116/+2861
git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6 * 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (74 commits) PCI: make msi_free_irqs() to use msix_mask_irq() instead of open coded write PCI: Fix the NIU MSI-X problem in a better way PCI ASPM: remove get_root_port_link PCI ASPM: cleanup pcie_aspm_sanity_check PCI ASPM: remove has_switch field PCI ASPM: cleanup calc_Lx_latency PCI ASPM: cleanup pcie_aspm_get_cap_device PCI ASPM: cleanup clkpm checks PCI ASPM: cleanup __pcie_aspm_check_state_one PCI ASPM: cleanup initialization PCI ASPM: cleanup change input argument of aspm functions PCI ASPM: cleanup misc in struct pcie_link_state PCI ASPM: cleanup clkpm state in struct pcie_link_state PCI ASPM: cleanup latency field in struct pcie_link_state PCI ASPM: cleanup aspm state field in struct pcie_link_state PCI ASPM: fix typo in struct pcie_link_state PCI: drivers/pci/slot.c should depend on CONFIG_SYSFS PCI: remove redundant __msi_set_enable() PCI PM: consistently use type bool for wake enable variable x86/ACPI: Correct maximum allowed _CRS returned resources and warn if exceeded ...
2009-06-19PCI: make msi_free_irqs() to use msix_mask_irq() instead of open coded writeHidetoshi Seto1-4/+1
Use msix_mask_irq() instead of direct use of writel, so as not to clear preserved bits in the Vector Control register [31:1]. Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-19PCI: Fix the NIU MSI-X problem in a better wayMatthew Wilcox1-18/+28
The previous MSI-X fix (8d181018532dd709ec1f789e374cda92d7b01ce1) had three bugs. First, it didn't move the write that disabled the vector. This led to writing garbage to the MSI-X vector (spotted by Michael Ellerman). It didn't fix the PCI resume case, and it had a race window where the device could generate an interrupt before the MSI-X registers were programmed (leading to a DMA to random addresses). Fortunately, the MSI-X capability has a bit to mask all the vectors. By setting this bit instead of clearing the enable bit, we can ensure the device will not generate spurious interrupts. Since the capability is now enabled, the NIU device will not have a problem with the reads and writes to the MSI-X registers being in the original order in the code. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Reviewed-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-18PCI ASPM: remove get_root_port_linkKenji Kaneshige1-13/+11
By having a pointer to the root port link, we can remove loops in get_root_port_link() to search the root port link. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-18PCI ASPM: cleanup pcie_aspm_sanity_checkKenji Kaneshige1-12/+9
Minor cleanup for pcie_aspm_sanity_check(). Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-18PCI ASPM: remove has_switch fieldKenji Kaneshige1-4/+1
We don't need the 'has_switch' field in the struct pcie_link_state. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-18PCI ASPM: cleanup calc_Lx_latencyKenji Kaneshige1-39/+34
Cleanup for calc_L0S_latency() and calc_L1_latency(). - Separate exit latency and acceptable latency calculation. - Some minor cleanups. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-18PCI ASPM: cleanup pcie_aspm_get_cap_deviceKenji Kaneshige1-5/+4
Minor cleanup for pcie_aspm_get_cap_device(). Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-18PCI ASPM: cleanup clkpm checksKenji Kaneshige1-14/+20
In the current ASPM implementation, callers of pcie_set_clock_pm() check Clock PM capability of the link or current Clock PM state of the link. This check should be done in pcie_set_clock_pm() itself. This patch moves those checks into pcie_set_clock_pm(). It also introduces pcie_set_clkpm_nocheck() that is equivalent to old pcie_set_clock_pm(), for the caller who wants to change Clocl PM state regardless of the Clock PM capability or current Clock PM state. In addition, this patch changes the function name from pcie_set_clock_pm() to pcie_set_clkpm() for consistency. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-18PCI ASPM: cleanup __pcie_aspm_check_state_oneKenji Kaneshige1-42/+25
Clean up and simplify __pcie_aspm_check_state_one(). Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-18PCI ASPM: cleanup initializationKenji Kaneshige1-67/+75
Clean up ASPM initialization by refactoring some functionality, renaming functions, and moving things around. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-18PCI ASPM: cleanup change input argument of aspm functionsKenji Kaneshige1-199/+173
In the current ASPM implementation, there are many functions that take a pointer to struct pci_dev corresponding to the upstream component of the link as a parameter. But, since those functions handle PCI express link state, a pointer to struct pcie_link_state is more suitable than a pointer to struct pci_dev. Changing a parameter to a pointer to struct pcie_link_state makes ASPM code much simpler and easier to read. This patch also contains some minor cleanups. This patch doesn't have any functional change. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-18PCI ASPM: cleanup misc in struct pcie_link_stateKenji Kaneshige1-9/+9
Cleanup for some fields in pcie_link_state. - Add comments. - make "downstream_has_switch" field 1-bit. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-18PCI ASPM: cleanup clkpm state in struct pcie_link_stateKenji Kaneshige1-19/+18
The "clk_pm_capable", "clk_pm_enable" and "bios_clk_state" fields in the struct pcie_link_state only take 1-bit value. So those fields don't need to be defined as unsigned int. This patch makes those fields 1-bit, and cleans up some related code. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-18PCI ASPM: cleanup latency field in struct pcie_link_stateKenji Kaneshige1-38/+28
Clean up latency related data structures for ASPM. - Introduce struct acpi_latency for exit latency and acceptable latency management. With this change, struct endpoint_state is no longer needed. - We don't need to hold both upstream latency and downstream latency in the current implementation. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-18PCI ASPM: cleanup aspm state field in struct pcie_link_stateKenji Kaneshige1-33/+38
The "support_state", "enabled_state" and "bios_aspm_state" fields in the struct pcie_link_state take 2-bit value. So those fields don't need to be defined as unsigned int. This patch makes those fields 2-bit, and cleans up some related code. Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2009-06-18PCI ASPM: fix typo in struct pcie_link_stateKenji Kaneshige1-7/+7
Fix a typo in struct pcie_link_state. The "sibiling" field in the struct pcie_link_state should be "sibling". Acked-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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