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path: root/drivers/net/wireless/ath/ath10k/rx_desc.h
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2019-02-20ath10k: switch to use SPDX license identifiersKalle Valo1-12/+1
Use SPDX identifiers everywhere in ath10k. Makefile was incorrectly marked in commit b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license"), fix that as well. Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2018-12-20ath10k: fix warning due to msdu limit errorBhagavathi Perumal S1-0/+7
Some hardwares variants (QCA99x0) are limiting msdu deaggregation with some threshold value(default limit in QCA99x0 is 64 msdus), it was introduced to avoid excessive MSDU-deaggregation in error cases. When number of sub frames exceeds the limit, target hardware will send all msdus starting from present msdu in RAW format as a single msdu packet and it will be indicated with error status bit "RX_MSDU_END_INFO0_MSDU_LIMIT_ERR" set in rx descriptor. This msdu frame is a partial raw MSDU and does't have first msdu and ieee80211 header. It caused below warning message. [ 320.151332] ------------[ cut here ]------------ [ 320.155006] WARNING: CPU: 0 PID: 3 at drivers/net/wireless/ath/ath10k/htt_rx.c:1188 In our issue case, MSDU limit error happened due to FCS error and generated this warning message. This fixes the warning by handling the MSDU limit error. If msdu limit error happens, driver adds first MSDU's ieee80211 header and sets A-MSDU present bit in QOS header so that upper layer processes this frame if it is valid or drop it if FCS error set. And removed the warning message, hence partial msdus without first msdu is expected in msdu limit error cases. Tested on QCA9984, Firmware 10.4-3.6-00104 Signed-off-by: Bhagavathi Perumal S <bperumal@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2018-09-06ath10k: htt: High latency RX supportErik Stromdahl1-0/+15
Special HTT RX handling for high latency interfaces. Since no DMA physical addresses are used in the RX ring config message (this is not supported by the high latency devices), no RX ring is allocated. All RX skb's are allocated by the driver and passed directly to mac80211 in the HTT RX indication handler. A nice side effect of this is that no huge buffer will be allocated with dma_alloc_coherent. On embedded systems with limited memory resources, the allocation of the RX ring is prone to fail. Some tweaks made to "make it work": Removal of protected bit in 802.11 header frame control field. The chipset seems to do hw decryption but the frame_control protected bit is still set. This is necessary for mac80211 not to drop the frame. Signed-off-by: Erik Stromdahl <erik.stromdahl@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2018-05-12ath10k: replace bit shifts with the BIT() macro for rx desc bitsGovind Singh1-67/+69
Use the BIT() macro from 'linux/bitops.h' to define the rx desc bit flags to have consistency with new definitions. Signed-off-by: Govind Singh <govinds@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
2017-12-27ath10k: update copyright yearKalle Valo1-1/+1
Update year for Qualcomm Atheros, Inc. copyrights. Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2017-12-27ath10k: Update rx descriptor for WCN3990 targetGovind Singh1-0/+50
WCN3990 rx descriptor uses different offset of msdu start, msdu end, ppdu end, rx pkt end and rx frag info. To accommodate different offsets, define respective fields in rx descriptor of WCN3990 target. Signed-off-by: Govind Singh <govinds@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2017-10-30ath10k: rebuild crypto header in rx data framesVasanthakumar Thiagarajan1-0/+3
Rx data frames notified through HTT_T2H_MSG_TYPE_RX_IND and HTT_T2H_MSG_TYPE_RX_FRAG_IND expect PN/TSC check to be done on host (mac80211) rather than firmware. Rebuild cipher header in every received data frames (that are notified through those HTT interfaces) from the rx_hdr_status tlv available in the rx descriptor of the first msdu. Skip setting RX_FLAG_IV_STRIPPED flag for the packets which requires mac80211 PN/TSC check support and set appropriate RX_FLAG for stripped crypto tail. Hw QCA988X, QCA9887, QCA99X0, QCA9984, QCA9888 and QCA4019 currently need the rebuilding of cipher header to perform PN/TSC check for replay attack. Please note that removing crypto tail for CCMP-256, GCMP and GCMP-256 ciphers in raw mode needs to be fixed. Since Rx with these ciphers in raw mode does not work in the current form even without this patch and removing crypto tail for these chipers needs clean up, raw mode related issues in CCMP-256, GCMP and GCMP-256 can be addressed in follow up patches. Tested-by: Manikanta Pubbisetty <mpubbise@qti.qualcomm.com> Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2017-04-05ath10k: clean header files from bad block commentsMarcin Rokicki1-5/+8
Fix output from checkpatch.pl like: Block comments use a trailing */ on a separate line Signed-off-by: Marcin Rokicki <marcin.rokicki@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-06-14ath10k: remove duplicate and unused rx rate flagsMohammed Shafi Shajakhan1-39/+0
All these flags are not used and their use is completely covered by 'ath10k_hw_rate_ofdm', 'ath10k_hw_rate_cck', and RX_PPDU_START_RATE_FLAG Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-05-24ath10k: define rx_ppdu_end for QCA9984Vasanthakumar Thiagarajan1-0/+46
QCA9984 Rx descriptor has two 32-bit words of location information when compared to one 32-bit word in QCA99X0. To handle this difference in rx descriptor ppdu_end, define a new ppdu_end for QCA9984 descriptor which has the new structure to represent rx_location_info. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2016-05-24ath10k: move rx_location_info out of struct rx_pkt_endVasanthakumar Thiagarajan1-1/+1
Define rx_location_info in struct rx_ppdu_end_qca99x0 after rx_pkt_end. This is to prepare rx_ppdu_end for QCA9984 chip. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-07-24ath10k: add support for qca99x0 Rx descriptorsPeter Oh1-3/+160
QCA99X0 chip has an extra 4 bytes in rx_msdu_start, 20 bytes in rx_msdu_end and 20 bytes in rx_ppdu_end structure which are used in htt_rx_desc and HTT Rx ring offset setup. This is necessary for correct Rx for QCA99X0 or Rx descriptors will be overwritten and corrupted. With this patch QCA988X and QCA6174 will have extra 44 bytes padding in Rx descriptor layout which is harmless. Signed-off-by: Peter Oh <poh@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-07-24ath10k: redefine rx_ppdu_end_common structure to cover qca99x0Peter Oh1-3/+7
rx_ppdu_end_common structure is valid for both of qca998x and qca6174, but not for qca99x0 since it has new additional members. Hence update the common structure to cover qca99x0 as well. Signed-off-by: Peter Oh <poh@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-03-30ath10k: add hw rate definitionsMichal Kazior1-0/+22
Prepare defines for future use. Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2015-01-27ath10k: add support for qca6174 Rx descriptorsMichal Kazior1-1/+24
The QCA6174 chip has an extra 4 bytes in rx_ppdu_end structure which is used in htt_rx_desc and HTT Rx ring offset setup. This is necessary for correct Rx for QCA6174 (otherwise Rx descriptors are overwritten and corrupted). This means QCA988X will have an extra 4 byte padding in Rx descriptor layout which is harmless. Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2014-09-18ath10k: fix use of multiple blank linesKalle Valo1-1/+0
Fixes checkpatch warnings: CHECK: Please don't use multiple blank lines Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2013-09-26ath10k: document decap modesMichal Kazior1-2/+22
Clarify how each decap mode works in one place. Signed-off-by: Michal Kazior <michal.kazior@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
2013-06-12ath10k: mac80211 driver for Qualcomm Atheros 802.11ac CQA98xx devicesKalle Valo1-0/+990
Here's a new mac80211 driver for Qualcomm Atheros 802.11ac QCA98xx devices. A major difference from ath9k is that there's now a firmware and that's why we had to implement a new driver. The wiki page for the driver is: http://wireless.kernel.org/en/users/Drivers/ath10k The driver has had many authors, they are listed here alphabetically: Bartosz Markowski <bartosz.markowski@tieto.com> Janusz Dziedzic <janusz.dziedzic@tieto.com> Kalle Valo <kvalo@qca.qualcomm.com> Marek Kwaczynski <marek.kwaczynski@tieto.com> Marek Puzyniak <marek.puzyniak@tieto.com> Michal Kazior <michal.kazior@tieto.com> Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
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