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path: root/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
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2022-08-05octeontx2-af: Fix mcam entry resource leakSubbaraya Sundeep1-0/+6
The teardown sequence in FLR handler returns if no NIX LF is attached to PF/VF because it indicates that graceful shutdown of resources already happened. But there is a chance of all allocated MCAM entries not being freed by PF/VF. Hence free mcam entries even in case of detached LF. Fixes: c554f9c1574e ("octeontx2-af: Teardown NPA, NIX LF upon receiving FLR") Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-07-11octeontx2-af: Drop rules for NPC MCAMRatheesh Kannoth1-0/+6
NPC exact match table installs drop on hit rules in NPC mcam for each channel. This rule has broadcast and multicast bits cleared. Exact match bit cleared and channel bits set. If exact match table hit bit is 0, corresponding NPC mcam drop rule will be hit for the packet and will be dropped. Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-07-11octeontx2-af: FLR handler for exact match table.Ratheesh Kannoth1-0/+3
FLR handler should remove/free all exact match table resources corresponding to each interface. Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-07-11octeontx2-af: Exact match supportRatheesh Kannoth1-0/+2
CN10KB silicon has support for exact match table. This table can be used to match maimum 64 bit value of KPU parsed output. Hit/non hit in exact match table can be used as a KEX key to NPC mcam. This patch makes use of Exact match table to increase number of DMAC filters supported. NPC mcam is no more need for each of these DMAC entries as will be populated in Exact match table. This patch implements following 1. Initialization of exact match table only for CN10KB. 2. Add/del/update interface function for exact match table. Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-07-11octeontx2-af: Use hashed field in MCAM keyRatheesh Kannoth1-0/+5
CN10KB variant of CN10K series of silicons supports a new feature where in a large protocol field (eg 128bit IPv6 DIP) can be condensed into a small hashed 32bit data. This saves a lot of space in MCAM key and allows user to add more protocol fields into the filter. A max of two such protocol data can be hashed. This patch adds support for hashing IPv6 SIP and/or DIP. Signed-off-by: Suman Ghosh <sumang@marvell.com> Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-07-06Revert "Merge branch 'octeontx2-af-next'"Jakub Kicinski1-16/+0
This reverts commit 2ef8e39f58f08589ab035223c2687830c0eba30f, reversing changes made to e7ce9fc9ad38773b660ef663ae98df4f93cb6a37. There are build warnings here which break the normal build due to -Werror. Ratheesh was nice enough to quickly follow up with fixes but didn't hit all the warnings I see on GCC 12 so to unlock net-next from taking patches let get this series out for now. Link: https://lore.kernel.org/r/20220707013201.1372433-1-kuba@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-07-06octeontx2-af: Drop rules for NPC MCAMRatheesh Kannoth1-0/+6
NPC exact match table installs drop on hit rules in NPC mcam for each channel. This rule has broadcast and multicast bits cleared. Exact match bit cleared and channel bits set. If exact match table hit bit is 0, corresponding NPC mcam drop rule will be hit for the packet and will be dropped. Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-06octeontx2-af: FLR handler for exact match table.Ratheesh Kannoth1-0/+3
FLR handler should remove/free all exact match table resources corresponding to each interface. Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-06octeontx2-af: Exact match supportRatheesh Kannoth1-0/+2
CN10KB silicon has support for exact match table. This table can be used to match maimum 64 bit value of KPU parsed output. Hit/non hit in exact match table can be used as a KEX key to NPC mcam. This patch makes use of Exact match table to increase number of DMAC filters supported. NPC mcam is no more need for each of these DMAC entries as will be populated in Exact match table. This patch implements following 1. Initialization of exact match table only for CN10KB. 2. Add/del/update interface function for exact match table. Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-07-06octeontx2-af: Use hashed field in MCAM keyRatheesh Kannoth1-0/+5
CN10KB variant of CN10K series of silicons supports a new feature where in a large protocol field (eg 128bit IPv6 DIP) can be condensed into a small hashed 32bit data. This saves a lot of space in MCAM key and allows user to add more protocol fields into the filter. A max of two such protocol data can be hashed. This patch adds support for hashing IPv6 SIP and/or DIP. Signed-off-by: Suman Ghosh <sumang@marvell.com> Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-01-21octeontx2-af: Retry until RVU block reset completeGeetha sowjanya1-2/+5
Few RVU blocks like SSO require more time for reset on some silicons. Hence retrying the block reset until success. Fixes: c0fa2cff8822c ("octeontx2-af: Handle return value in block reset") Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-12-01octeontx2-af: Fix a memleak bug in rvu_mbox_init()Zhou Qingyang1-1/+1
In rvu_mbox_init(), mbox_regions is not freed or passed out under the switch-default region, which could lead to a memory leak. Fix this bug by changing 'return err' to 'goto free_regions'. This bug was found by a static analyzer. The analysis employs differential checking to identify inconsistent security operations (e.g., checks or kfrees) between two code paths and confirms that the inconsistent operations are not recovered in the current function or the callers, so they constitute bugs. Note that, as a bug found by static analysis, it can be a false positive or hard to trigger. Multiple researchers have cross-reviewed the bug. Builds with CONFIG_OCTEONTX2_AF=y show no new warnings, and our static analyzer no longer warns about this code. Fixes: 98c561116360 (“octeontx2-af: cn10k: Add mbox support for CN10K platform”) Signed-off-by: Zhou Qingyang <zhou1615@umn.edu> Link: https://lore.kernel.org/r/20211130165039.192426-1-zhou1615@umn.edu Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-10-14octeontx2-af: Perform cpt lf teardown in non FLR pathNithin Dabilpuram1-1/+2
Perform CPT LF teardown in non FLR path as well via cpt_lf_free() Currently CPT LF teardown and reset sequence is only done when FLR is handled with CPT LF still attached. This patch also fixes cpt_lf_alloc() to set EXEC_LDWB in CPT_AF_LFX_CTL2 when being completely overwritten as that is the default value and is better for performance. Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-10-14octeontx2-af: Enable CPT HW interruptsSrujana Challa1-0/+13
This patch enables and registers interrupt handler for CPT HW interrupts. Signed-off-by: Srujana Challa <schalla@marvell.com> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-10-10ethernet: Remove redundant 'flush_workqueue()' callsChristophe JAILLET1-2/+0
'destroy_workqueue()' already drains the queue before destroying it, so there is no need to flush it explicitly. Remove the redundant 'flush_workqueue()' calls. This was generated with coccinelle: @@ expression E; @@ - flush_workqueue(E); destroy_workqueue(E); Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Leon Romanovsky <leonro@nvidia.com> #mlx* Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-28octeontx2-af: Add external ptp input clockYi Guo1-1/+2
PTP hardware block can be configured to utilize the external clock. Also the current ptp timestamp can be captured when external trigger is applied on a gpio pin. These features are required in scenarios like connecting a external timing device to the chip for time synchronization. The timing device provides the clock and trigger(PPS signal) to the PTP block. This patch does the following: 1. configures PTP block to use external clock frequency and timestamp capture on external event. 2. sends PTP_REQ_EXTTS events to kernel ptp phc susbsytem with captured timestamps 3. aligns PPS edge to adjusted ptp clock in the ptp device by setting the PPS_THRESH to the reminder of the last timestamp value captured by external PPS Signed-off-by: Yi Guo <yig@marvell.com> Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-28octeontx2-af: Use ptp input clock info from firmware dataSubbaraya Sundeep1-0/+3
The input clock frequency of PTP block is figured out from hardware reset block currently. The firmware data already has this info in sclk. Hence simplify ptp driver to use sclk from firmware data. Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-17octeontx2-af: Remove redundant initialization of variable blkaddrColin Ian King1-1/+1
The variable blkaddr is being initialized with a value that is never read, it is being updated later on in a for-loop. The assignment is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-16octeontx2-af: Hardware configuration for inline IPsecSrujana Challa1-0/+54
On OcteonTX2/CN10K SoC, the admin function (AF) is the only one with all priviliges to configure HW and alloc resources, PFs and it's VFs have to request AF via mailbox for all their needs. This patch adds new mailbox messages for CPT PFs and VFs to configure HW resources for inline-IPsec. Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Srujana Challa <schalla@marvell.com> Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-04octeontx2-af: Add a 'rvu_free_bitmap()' functionChristophe JAILLET1-0/+5
In order to match 'rvu_alloc_bitmap()', add a 'rvu_free_bitmap()' function Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-09-01octeontx2-af: Add additional register check to rvu_poll_reg()Smadar Fuks1-1/+11
Check one more time before exiting the API with an error. Fix API to poll at least twice, in case there are other high priority tasks and this API doesn't get CPU cycles for multiple jiffies update. In addition, increase timeout from usecs_to_jiffies(10000) to usecs_to_jiffies(20000), to prevent the case that for CONFIG_100HZ timeout will be a single jiffies. A single jiffies results actual timeout that can be any time between 1usec and 10msec. To solve this, a value of usecs_to_jiffies(20000) ensures that timeout is 2 jiffies. Signed-off-by: Smadar Fuks <smadarf@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-08-29octeontx2-af: Fix inconsistent license textSunil Goutham1-5/+2
Fixed inconsistent license text across the RVU admin function driver. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-08-25octeontx2-af: Add free rsrc count mbox msgGeorge Cherian1-0/+93
Upon receiving the MBOX_MSG_FREE_RSRC_CNT, the AF will find out the current number of free resources and reply it back to the requester. No guarantee is given on the future state of the free resources yet. If another requester sends MBOX_MSG_ATTACH_RESOURCES after this call, the number of available resources might change. Signed-off-by: George Cherian <george.cherian@marvell.com> Signed-off-by: Stanislaw Kardach <skardach@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-08-25octeontx2-af: Add SDP interface supportRadha Mohan Chintakuntla1-1/+12
Added support for packet IO via SDK links which is used when Octeon is connected as a end-point. Traffic host to end-point and vice versa flow through SDP links. This patch also support dual SDP blocks supported in 98xx silicon. Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com> Signed-off-by: Nalla Pradeep <pnalla@marvell.com> Signed-off-by: Subrahmanyam Nilla <snilla@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-08-25octeontx2-af: enable tx shaping feature for 96xx C0Nithin Dabilpuram1-2/+5
Starting from 96xx C0 onwards all silicons support traffic shaping. This patch enables that feature along with other changes - When PIR/CIR shaping config is modified, toggle SW_XOFF for config to take effect - Before SMQ flush, clear SW_XOFF at all parent schedulers - Support to read current transmit scheduler configuration via mbox Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-08-25octeontx2-af: Change the order of queue work and interrupt disableNithin Dabilpuram1-4/+5
Clear and disable interrupt before queueing work as there might be a chance that work gets completed on other core faster and interrupt enable as a part of the work completes before interrupt disable in the interrupt context. This leads to permanent disable of interrupt. Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-08-22octeontx2-af: Handle return value in block reset.Geetha sowjanya1-1/+4
Print debug message if any of the RVU hardware blocks reset fails. Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-08-19octeontx2-af: remove redudant second error check on variable errColin Ian King1-2/+0
A recent change added error checking messages and failed to remove one of the previous error checks. There are now two checks on variable err so the second one is redundant dead code and can be removed. Addresses-Coverity: ("Logically dead code") Fixes: a83bdada06bf ("octeontx2-af: Add debug messages for failures") Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20210818130927.33895-1-colin.king@canonical.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-08-17octeontx2-af: Add debug messages for failuresSunil Goutham1-19/+73
Added debug messages for various failures during probe. This will help in quickly identifying the API where the failure is happening. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-07-23octeontx2-af: Fix uninitialized variables in rvu_switchSubbaraya Sundeep1-2/+4
Get the number of VFs of a PF correctly by calling rvu_get_pf_numvfs in rvu_switch_disable function. Also hwvf is not required hence remove it. Fixes: 23109f8dd06d ("octeontx2-af: Introduce internal packet switching") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-07-19octeontx2-af: Introduce internal packet switchingSubbaraya Sundeep1-1/+3
As of now any communication between CGXs PFs and their VFs within the system is possible only by external switches sending packets back to the system. This patch adds internal switching support. Broadcast packet replication is not covered here. RVU admin function (AF) maintains MAC addresses of all interfaces in the system. When switching is enabled, MCAM entries are allocated to install rules such that packets with DMAC matching any of the internal interface MAC addresses is punted back into the system via the loopback channel. On the receive side the default unicast rules are modified to not check for ingress channel. So any packet with matching DMAC irrespective of which interface it is coming from will be forwarded to the respective PF/VF interface. The transmit side rules and default unicast rules are updated if user changes MAC address of an interface. Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-07-19octeontx2-af: Enable transmit side LBK linkSubbaraya Sundeep1-0/+6
For enabling VF-VF switching the packets egressing out of CGX mapped VFs needed to be sent to LBK so that same packets are received back to the system. But the LBK link also needs to be enabled in addition to a VF's mapped CGX_LMAC link otherwise hardware raises send error interrupt indicating selected LBK link is not enabled in NIX_AF_TL3_TL2X_LINKX_CFG register. Hence this patch enables all LBK links in TL3_TL2_LINKX_CFG registers. Also to enable packet flow between PFs/VFs of NIX0 to PFs/VFs of NIX1(in 98xx silicon) the NPC TX DMAC rules has to be installed such that rules must be hit for any TX interface i.e., NIX0-TX or NIX1-TX provided DMAC match creteria is met. Hence this patch changes the behavior such that MCAM is programmed to match with any NIX0/1-TX interface for TX rules. Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-07-01octeontx2-af: cn10k: Setting up lmtst map tableHarman Kalra1-0/+1
Introducing a new mailbox to support updating lmt entries and common lmt base address scheme i.e. multiple pcifuncs can share lmt region to reduce L1 cache pressure for application. Parameters passed to mailbox includes the primary pcifunc value whose lmt regions will be shared by other secondary pcifuncs. Here secondary pcifunc will be the one who is calling the mailbox. For example: By default each pcifunc has its own LMT base address: PCIFUNC1 LMT_BASE_ADDR A PCIFUNC2 LMT_BASE_ADDR B PCIFUNC3 LMT_BASE_ADDR C PCIFUNC4 LMT_BASE_ADDR D Application will choose PCIFUNC1 as base/primary pcifunc and as and when other pcifunc(secondary pcifuncs) gets probed, this mailbox will be called and LMTST table will be updated as: PCIFUNC1 LMT_BASE_ADDR A PCIFUNC2 LMT_BASE_ADDR A PCIFUNC3 LMT_BASE_ADDR A PCIFUNC4 LMT_BASE_ADDR A On FLR lmtst map table gets resetted to the default lmt base addresses for all secondary pcifuncs. Signed-off-by: Harman Kalra <hkalra@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-15octeontx2-af: cn10k: Debugfs support for bandwidth profilesSunil Goutham1-0/+8
Added support for dumping current resource status of bandwidth profiles and contexts of allocated profiles via debugfs. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-11octeontx2-af: add new mailbox to configure VF trust modeHariprasad Kelam1-0/+42
Add new mailbox to enable PF to configure VF as trusted VF. Trusted VF feature allows VFs to perform priviliged operations such as enabling VF promiscuous mode, all-multicast mode and changing the VF MAC address configured by PF. Refactored the VF interface flags maintained by the AF driver such that the flags do not overlap for various configurations. Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <Sunil.Goutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-05-29octeontx2-af: add support for custom KPU entriesStanislaw Kardach1-0/+6
Add ability to load a set of custom KPU entries. This allows for flexible support for custom protocol parsing. AF driver will attempt to load the profile and verify if it can fit hardware capabilities. If not, it will revert to the built-in profile. Next it will replace the first KPU_MAX_CST_LT (2) entries in each KPU in default profile with entries read from the profile image. The built-in profile should always contain KPU_MAX_CSR_LT first no-match entries and AF driver will disable those in the KPU unless custom profile is loaded. Profile file contains also a list of default protocol overrides to allow for custom protocols to be used there. Signed-off-by: Stanislaw Kardach <skardach@marvell.com> Signed-off-by: George Cherian <george.cherian@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-03-18octeontx2-af: Fix irq free in rvu teardownGeetha sowjanya1-2/+4
Current devlink code try to free already freed irqs as the irq_allocate flag is not cleared after free leading to kernel crash while removing rvu driver. The patch fixes the irq free sequence and clears the irq_allocate flag on free. Fixes: 7304ac4567bc ("octeontx2-af: Add mailbox IRQ and msg handlers") Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11octeontx2-af: cn10K: Add MTU configurationHariprasad Kelam1-1/+28
OcteonTx3 CN10K silicon supports bigger MTU when compared to 9216 MTU supported by OcteonTx2 silicon variants. Lookback interface supports upto 64K and RPM LMAC interfaces support upto 16K. This patch does the necessary configuration and adds support for PF/VF drivers to retrieve max packet size supported via mbox This patch also configures tx link credit by considering supported fifo size and max packet length for Octeontx3 silicon. This patch also removes platform specific name from the driver name. Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11octeontx2-af: cn10k: Add support for programmable channelsSubbaraya Sundeep1-2/+6
NIX uses unique channel numbers to identify the packet sources/sinks like CGX,LBK and SDP. The channel numbers assigned to each block are hardwired in CN9xxx silicon. The fixed channel numbers in CN9xxx are: 0x0 | a << 8 | b - LBK(0..3)_CH(0..63) 0x0 | a << 8 - Reserved 0x700 | a - SDP_CH(0..255) 0x800 | a << 8 | b << 4 | c - CGX(0..7)_LMAC(0..3)_CH(0..15) All the channels in the above fixed enumerator(with maximum number of blocks) are not required since some chips have less number of blocks. For CN10K silicon the channel numbers need to be programmed by software in each block with the base channel number and range of channels. This patch calculates and assigns the channel numbers to efficiently distribute the channel number range(0-4095) among all the blocks. The assignment is made based on the actual number of blocks present and also contiguously leaving no holes. The channel numbers remaining after the math are used as new CPT replay channels present in CN10K. Also since channel numbers are not fixed the transmit channel link number needed by AF consumers is calculated by AF and sent along with nix_lf_alloc mailbox response. Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-11octeontx2-af: cn10k: Add mbox support for CN10K platformSubbaraya Sundeep1-27/+95
Firmware allocates memory regions for PFs and VFs in DRAM. The PFs memory region is used for AF-PF and PF-VF mailbox. This mbox facilitates communication between AF-PF and PF-VF. On CN10K platform: The DRAM region allocated to PF is enumerated as PF BAR4 memory. PF BAR4 contains AF-PF mbox region followed by its VFs mbox region. AF-PF mbox region base address is configured at RVU_AF_PFX_BAR4_ADDR PF-VF mailbox base address is configured at RVU_PF(x)_VF_MBOX_ADDR = RVU_AF_PF()_BAR4_ADDR+64KB. PF access its mbox region via BAR4, whereas VF accesses PF-VF DRAM mailboxes via BAR2 indirect access. On CN9XX platform: Mailbox region in DRAM is divided into two parts AF-PF mbox region and PF-VF mbox region i.e all PFs mbox region is contiguous similarly all VFs. The base address of the AF-PF mbox region is configured at RVU_AF_PF_BAR4_ADDR. AF-PF1 mbox address can be calculated as RVU_AF_PF_BAR4_ADDR * mbox size. The base address of PF-VF mbox region for each PF is configure at RVU_AF_PF(0..15)_VF_BAR4_ADDR.PF access its mbox region via BAR4 and its VF mbox regions from RVU_PF_VF_BAR4_ADDR register, whereas VF access its mbox region via BAR4. This patch changes mbox initialization to support both CN9XX and CN10K platform. This patch also adds CN10K PTP subsystem and device IDs to ptp driver id table. Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-02-03octeontx2-af: Handle CPT function level resetSrujana Challa1-0/+3
When FLR is initiated for a VF (PCI function level reset), the parent PF gets a interrupt. PF then sends a message to admin function (AF), which then cleans up all resources attached to that VF. This patch adds support to handle CPT FLR. Signed-off-by: Narayana Prasad Raju Atherya <pathreya@marvell.com> Signed-off-by: Suheil Chandran <schandran@marvell.com> Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Signed-off-by: Srujana Challa <schalla@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-01-28octeontx2-af: Fix 'physical' typosBjorn Helgaas1-1/+1
Fix misspellings of "physical". Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Willem de Bruijn <willemb@google.com> Link: https://lore.kernel.org/r/20210127181359.3008316-1-helgaas@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2021-01-19octeontx2-af: Remove unneeded semicolonsXu Wang1-1/+1
fix semicolon.cocci warnings: ./drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c:272:2-3: Unneeded semicolon drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c:1788:3-4: Unneeded semicolon drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c:1809:3-4: Unneeded semicolon drivers/net/ethernet/marvell/octeontx2/af/rvu.c:1326:2-3: Unneeded semicolon Signed-off-by: Xu Wang <vulab@iscas.ac.cn> Link: https://lore.kernel.org/r/20210119075059.17493-1-vulab@iscas.ac.cn Link: https://lore.kernel.org/r/20210119075507.17699-1-vulab@iscas.ac.cn Link: https://lore.kernel.org/r/20210119080037.17931-1-vulab@iscas.ac.cn Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-12-14octeontx2-af: Add devlink suppoort to af driverGeorge Cherian1-1/+8
Add devlink support to AF driver. Basic devlink support is added. Currently info_get is the only supported devlink ops. devlink ouptput looks like this # devlink dev pci/0002:01:00.0 # devlink dev info pci/0002:01:00.0: driver octeontx2-af # Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com> Signed-off-by: Jerin Jacob <jerinj@marvell.com> Signed-off-by: George Cherian <george.cherian@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-17octeontx2-af: Handle PF-VF mac address changesHariprasad Kelam1-1/+11
This patch handles the VF mac address changes as given below. 1. mac addr configrued by VF will be retained until VF module unload. 2. mac addr configred by PF for VF will be retained until power cycle. 3. mac addr confgired by PF for its VF can't be overwritten by VF. Signed-off-by: Hariprasad Kelam <hkelam@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-11-17octeontx2-af: Verify MCAM entry channel and PF_FUNCSubbaraya Sundeep1-2/+2
This patch adds support to verify the channel number sent by mailbox requester before writing MCAM entry for Ingress packets. Similarly for Egress packets, verifying the PF_FUNC sent by the mailbox user. Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Kiran Kumar K <kirankumark@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-10-31octeontx2-af: Mbox changes for 98xxSubbaraya Sundeep1-16/+69
This patch puts together all mailbox changes for 98xx silicon: Attach -> Modify resource attach mailbox handler to request LFs from a block address out of multiple blocks of same type. If a PF/VF need LFs from two blocks of same type then attach mbox should be called twice. Example: struct rsrc_attach *attach; .. Allocate memory for message .. attach->cptlfs = 3; /* 3 LFs from CPT0 */ .. Send message .. .. Allocate memory for message .. attach->modify = 1; attach->cpt_blkaddr = BLKADDR_CPT1; attach->cptlfs = 2; /* 2 LFs from CPT1 */ .. Send message .. Detach -> Update detach mailbox and its handler to detach resources from CPT1 and NIX1 blocks. MSIX -> Updated the MSIX mailbox and its handler to return MSIX offsets for the new block CPT1. Free resources -> Update free_rsrc mailbox and its handler to return the free resources count of new blocks NIX1 and CPT1 Links -> Number of CGX,LBK and SDP links may vary between platforms. For example, in 98xx number of CGX and LBK links are more than 96xx. Hence the info about number of links present in hardware is useful for consumers to request link configuration properly. This patch sends this info in nix_lf_alloc_rsp. Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-10-31octeontx2-af: Add NIX1 interfaces to NPCSubbaraya Sundeep1-0/+4
On 98xx silicon, NPC block has additional mcam entries, counters and NIX1 interfaces. Extended set of registers are present for the new mcam entries and counters. This patch does the following: - updates the register accessing macros to use extended set if present. - configures the MKEX profile for NIX1 interfaces also. - updates mcam entry write functions to use assigned NIX0/1 interfaces for the PF/VF. Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-10-31octeontx2-af: Map NIX block from CGX connectionSubbaraya Sundeep1-3/+58
Firmware configures NIX block mapping for all CGXs to achieve maximum throughput. This patch reads the configuration and create mapping between RVU PF and NIX blocks. And for LBK VFs assign NIX0 for even numbered VFs and NIX1 for odd numbered VFs. Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2020-10-31octeontx2-af: Initialize NIX1 blockRakesh Babu1-0/+2
This patch modifies NIX functions to operate with nix_hw context so that existing functions can be used for both NIX0 and NIX1 blocks. And the NIX blocks present in the system are initialized during driver init and freed during exit. Signed-off-by: Rakesh Babu <rsaladi2@marvell.com> Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 12:42:38 +0000