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2019-05-06spi-nor: intel-spi: Add support for Intel Comet Lake SPI serial flashMika Westerberg1-0/+1
Intel Comet Lake has the same SPI serial flash controller as Ice Lake. Add Comet Lake PCI ID to the driver list of supported devices. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-05-05Merge tag 'nand/for-5.2' of ↵Richard Weinberger67-2093/+3392
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux into mtd/next NAND core changes: - Support having the bad block markers in either the first, second or last page of a block. The combination of all three location is now possible. - Constification of NAND_OP_PARSER(_PATTERN) elements. - Generic NAND DT bindings changed to yaml format (can be used to check the proposed bindings. First platform to be fully supported: sunxi. - Stopped using several legacy hooks. - Preparation to use the generic NAND layer with the addition of several helpers and the removal of the struct nand_chip from generic functions. - Kconfig cleanup to prepare the introduction of external ECC engines support. - Fallthrough comments. - Introduction of the SPI-mem dirmap API for SPI-NAND devices. Raw NAND controller drivers changes: - nandsim: * Switch to ->exec-op(). - meson: * Misc cleanups and fixes. * New OOB layout. - Sunxi: * A23/A33 NAND DMA support. - Ingenic: * Full reorganization and cleanup. * Clear separation between NAND controller and ECC engine. * Support JZ4740 an JZ4725B. - Denali: * Clear controller/chip separation. * ->exec_op() migration. * Various cleanups. - fsl_elbc: * Enable software ECC support. - Atmel: * Sam9x60 support. - GPMI: * Introduce the GPMI_IS_MXS() macro. - Various trivial/spelling/coding style fixes.
2019-04-25mtd: rawnand: marvell: Clean the controller state before each operationMiquel Raynal1-6/+6
Since the migration of the driver to stop using the legacy ->select_chip() hook, there is nothing deselecting the target anymore, thus the selection is not forced at the next access. Ensure the ND_RUN bit and the interrupts are always in a clean state. Cc: Daniel Mack <daniel@zonque.org> Cc: stable@vger.kernel.org Fixes: b25251414f6e00 ("mtd: rawnand: marvell: Stop implementing ->select_chip()") Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Daniel Mack <daniel@zonque.org> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2019-04-18mtd: nandsim: switch to exec_op interfaceRichard Weinberger1-31/+47
Stop using the legacy interface. Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: nandsim: Embed struct nand_chip in struct nandsimRichard Weinberger1-25/+24
We will need struct nand_controller soon, so more stuff need to be parts of struct nandsim. While we are here, rename "nand" to "ns" to use the same naming scheme everywhere in nandsim. Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: AMD: Also use the last page for bad block markersFrieder Schrempf1-1/+7
According to the datasheet of some Cypress SLC NANDs, the bad block markers can be in the first, second or last page of a block. So let's check all three locations. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: ESMT: Also use the last page for bad block markersFrieder Schrempf1-1/+8
It is known that some ESMT SLC NANDs have been shipped with the factory bad block markers in the first or last page of the block, instead of the first or second page. To be on the safe side, let's check all three locations. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: Support bad block markers in first, second or last pageFrieder Schrempf3-37/+56
Currently supported bad block marker positions within the block are: * in first page only * in last page only * in first or second page Some ESMT NANDs are known to have been shipped by the manufacturer with bad block markers in the first or last page, instead of the first or second page. Also the datasheets for Cypress/Spansion/AMD NANDs claim that the first, second *and* last page needs to be checked. Therefore we make it possible to set NAND_BBM_FIRSTPAGE, NAND_BBM_SECONDPAGE and NAND_BBM_LASTPAGE independently in any combination. To simplify the code, the logic to evaluate the flags is moved to a a new function nand_bbm_get_next_page(). Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: nand: Make flags for bad block marker position more granularFrieder Schrempf10-11/+14
To be able to check and set bad block markers in the first and second page of a block independently of each other, we create separate flags for both cases. Previously NAND_BBM_SECONDPAGE meant, that both, the first and the second page were used. With this patch NAND_BBM_FIRSTPAGE stands for using the first page and NAND_BBM_SECONDPAGE for using the second page. This patch is only for preparation of subsequent changes and does not implement the logic to actually handle both flags separately. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: onenand: Store bad block marker position in chip structFrieder Schrempf2-4/+4
The information about where the manufacturer puts the bad block markers inside the bad block and in the OOB data is stored in different places. Let's move this information to the chip struct, as we did it for rawnand. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: Always store info about bad block markers in chip structFrieder Schrempf10-19/+19
The information about where the manufacturer puts the bad block markers inside the bad block and in the OOB data is stored in different places. Let's move this information to nand_chip.options and nand_chip.badblockpos. As this chip-specific information is not directly related to the bad block table (BBT), we also rename the flags to NAND_BBM_*. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: meson: only initialize the RB completion onceMartin Blumenstingl1-1/+2
Documentation/scheduler/completion.txt states: Calling init_completion() on the same completion object twice is most likely a bug as it re-initializes the queue to an empty queue and enqueued tasks could get "lost" - use reinit_completion() in that case, but be aware of other races. Initialize nfc->completion in meson_nfc_probe using init_completion and change the call in meson_nfc_queue_rb to reinit_completion so the logic matches what the documentation suggests. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by:Liang Yang <liang.yang@amlogic.com> Acked-by: Liang Yang <liang.yang@amlogic.com> Tested-by:Liang Yang <liang.yang@amlogic.com> Acked-by: Liang Yang <liang.yang@amlogic.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: meson: use a void pointer for meson_nfc_dma_buffer_setupMartin Blumenstingl1-5/+5
This simplifies the code because it gets rid of the casts to an u8-pointer when passing "info_buf" from struct meson_nfc_nand_chip. Also it gets rid of the cast of the u8 databuf pointer to a void pointer. The logic inside meson_nfc_dma_buffer_setup() doesn't care about the pointer types themselves because it only passes them to dma_map_single which accepts a void pointer. No functional changes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by:Liang Yang <liang.yang@amlogic.com> Acked-by: Liang Yang <liang.yang@amlogic.com> Tested-by:Liang Yang <liang.yang@amlogic.com> Acked-by: Liang Yang <liang.yang@amlogic.com> Tested-by:Liang Yang <liang.yang@amlogic.com> Acked-by: Liang Yang <liang.yang@amlogic.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: meson: use of_property_count_elems_of_size helperMartin Blumenstingl1-4/+1
Use the of_property_count_elems_of_size() helper instead of open-coding it's logic. As a bonus this will now error out if the "reg" property values use an incorrect size (anything other than sizeof(u32)). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by:Liang Yang <liang.yang@amlogic.com> Acked-by: Liang Yang <liang.yang@amlogic.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: meson: use struct_size macroMartin Blumenstingl1-2/+1
Use the recently introduced struct_size macro instead of open-coding it's logic. No functional changes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by:Liang Yang <liang.yang@amlogic.com> Acked-by: Liang Yang <liang.yang@amlogic.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: marvell: Fix helper name in commentMiquel Raynal1-1/+1
Since the migration of the driver to stop using the legacy ->select_chip() hook, the marvell_nfc_select_chip() helper has been 'renamed' to marvell_nfc_select_target(). Update a left-over reference to this helper in a comment in the ->resume() path. Fixes: b25251414f6e00 ("mtd: rawnand: marvell: Stop implementing ->select_chip()") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2019-04-18mtd: rawnand: sunxi: Add A23/A33 DMA supportMiquel Raynal1-2/+36
Allwinner NAND controllers can make use of DMA to enhance the I/O throughput thanks to ECC pipelining. DMA handling with A23/A33 NAND IP is a bit different than with the older SoCs, hence the introduction of a new compatible to handle: * the differences between register offsets, * the burst length change from 4 to minimum 8, * drive SRAM accesses through the AHB bus instead of the MBUS. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: sunxi: Add a platform data structureMiquel Raynal1-5/+32
Before the introduction of A33 NAND DMA support, let's use a platform data structure for parameters that will differ. Right now, there is only one compatible with one data structure. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: ingenic: Make jz4725b_ooblayout_ops staticYueHaibing1-1/+1
Fix sparse warning: drivers/mtd/nand/raw/ingenic/ingenic_nand.c:140:32: warning: symbol 'jz4725b_ooblayout_ops' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: ingenic: Add missing MODULE_* informationYueHaibing1-0/+3
gcc warning this: WARNING: modpost: missing MODULE_LICENSE() in drivers/mtd/nand/raw/ingenic/ingenic_ecc.o Add MODULE_LICENSE,MODULE_AUTHOR and MODULE_DESCRIPTION. Reported-by: Hulk Robot <hulkci@huawei.com> Fixes: 9df5741a577e ("mtd: rawnand: ingenic: Separate top-level and SoC specific code") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: denali: clean up coding styleMasahiro Yamada1-28/+26
Eliminate the following reports from 'scripts/checkpatch.pl --strict'. CHECK: Prefer kernel type 'u8' over 'uint8_t' CHECK: Prefer kernel type 'u32' over 'uint32_t' CHECK: Alignment should match open parenthesis I slightly changed denali_check_erased_page() to shorten it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: denali: remove DENALI_NR_BANKS macroMasahiro Yamada1-5/+4
Use the runtime-detected denali->nbanks instead of hard-coded DENALI_NR_BANKS (=4). The actual number of banks depends on the IP configuration, and can be less than DENALI_NR_BANKS. It is pointless to touch registers of unsupported banks. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: denali: decouple controller and NAND chipsMasahiro Yamada4-217/+455
Currently, this driver sticks to the legacy NAND model because it was upstreamed before commit 2d472aba15ff ("mtd: nand: document the NAND controller/NAND chip DT representation"). However, relying on the dummy_controller is already deprecated. Switch over to the new controller/chip representation. The struct denali_nand_info has been split into denali_controller and denali_chip, to contain the controller data, per-chip data, respectively. One problem is, this commit changes the DT binding. So, as always, the backward compatibility must be taken into consideration. In the new binding, the controller node expects #address-cells = <1>; #size-cells = <0>; ... since the child nodes represent NAND chips. In the old binding, the controller node may have subnodes, but they are MTD partitions. The denali_dt_is_legacy_binding() exploits it to distinguish old/new platforms. Going forward, the old binding is only allowed for existing DT files. I updated the binding document. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: denali_pci: rename goto labelsMasahiro Yamada1-4/+4
As Documentation/process/coding-style.rst says, choose label names which say what the goto does. The out_<action> label style is already used in denali_dt.c. Rename likewise for denali_pci.c Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: denali: use bool type instead of int where appropriateMasahiro Yamada2-13/+14
Use 'bool' type for the following boolean parameters. - write (write or read?) - dma_avail (DMA engine available or not?) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: denali: switch over to ->exec_op() from legacy hooksMasahiro Yamada1-108/+143
Implement ->exec_op(), and remove the deprecated hooks. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: denali: remove unneeded casts in denali_{read, write}_pioMasahiro Yamada1-7/+5
Since (u32 *) can accept an opaque pointer, the explicit casting from (void *) to (u32 *) is redundant. Change the function argument type to remove the casts. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: denali: refactor raw page accessorsMasahiro Yamada2-265/+182
The Denali IP adopts the syndrome page layout (payload and ECC are interleaved). The *_page_raw() and *_oob() callbacks are complicated because they must hide the underlying layout used by the hardware, and always return contiguous in-band and out-of-band data. The Denali IP cannot reuse nand_{read,write}_page_raw_syndrome() in nand_base.c because its hardware ECC engine skips some of first bytes in OOB. That is why this driver implements specially-crafted *_page_raw() and *_oob() hooks. Currently, similar code is duplicated to reorganize the data layout. For example, denali_read_page_raw() and denali_write_page_raw() look almost the same. The complexity is partly due to the DMA transfer used for better performance of *_page_raw() accessors. On second thought, we do not need to care about their performance because MTD_OPS_RAW is rarely used. Let's focus on code cleanups rather than the performance. This commit removes the internal buffer for DMA, and factors out as much code as possible. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: denali: use more nand_chip pointers for internal functionsMasahiro Yamada1-27/+34
With the recent refactoring, the NAND driver hooks now take a pointer to nand_chip. Add to_denali() in order to convert (struct nand_chip *) to (struct denali_nand_info *) directly. It is more useful than the current mtd_to_denali(). I changed some helper functions to take (struct nand_chip *). This will avoid pointer conversion back and forth, and ease further development. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: atmel: Fix spelling mistake in error messageMiquel Raynal1-1/+1
Wrong copy/paste from the previous block, the error message should refer to #size-cells instead of #address-cells. Fixes: f88fc122cc34 ("mtd: nand: Cleanup/rework the atmel_nand driver") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-04-18mtd: rawnand: fsl_elbc: Make SW ECC workMarek Behún1-18/+34
Move the code that choses ECC into _attach_chip, which is executed only after the chip->ecc.* properties were loaded from device-tree. This way we know which ECC method was chosen by the device-tree and can set methods appropriately. The chip->ecc.*page methods should be set to fsl_elbc_*page only in HW ECC mode. Signed-off-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: fsl_elbc: Implement RNDOUT commandMarek Behún1-0/+9
This is needed for SW ECC. Signed-off-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: fsl_elbc: Cosmetic moveMarek Behún1-73/+73
Move the fsl_elbc_attach_chip function after the definitions of fsl_elbc_read_page and friends in preparation for the next patch. Signed-off-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: fix build dependencyAnders Roxell2-2/+2
When enabling CONFIG_MTD_NAND_ECC_SW_BCH as a module, the MTD_NAND_ECC_SW_BCH depends on MTD_NAND, but the module controlled by MTD_NAND links against the module controlled by MTD_NAND_ECC_SW_BCH. This leads to the following link failure. aarch64-linux-gnu-ld: drivers/mtd/nand/raw/nand_base.o: in function `nand_cleanup': ../drivers/mtd/nand/raw/nand_base.c:5886: undefined reference to `nand_bch_free' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5886:(.text+0x9928): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `nand_bch_free' aarch64-linux-gnu-ld: drivers/mtd/nand/raw/nand_base.o: in function `nand_set_ecc_soft_ops': ../drivers/mtd/nand/raw/nand_base.c:5093: undefined reference to `nand_bch_calculate_ecc' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5093:(.text+0xe914): relocation truncated to fit: R_AARCH64_ADR_PREL_PG_HI21 against undefined symbol `nand_bch_calculate_ecc' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5093: undefined reference to `nand_bch_calculate_ecc' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5094: undefined reference to `nand_bch_correct_data' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5094:(.text+0xe934): relocation truncated to fit: R_AARCH64_ADR_PREL_PG_HI21 against undefined symbol `nand_bch_correct_data' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5094: undefined reference to `nand_bch_correct_data' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5148: undefined reference to `nand_bch_init' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5148:(.text+0xebbc): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `nand_bch_init' Rework CONFIG_MTD_NAND_ECC_SW_BCH from tristate to bool, and then link the nand_bch.o file into nand.ko if its enabled. Fixes: 51ef1d0b2095 ("mtd: nand: Clarify Kconfig entry for software BCH ECC algorithm") Signed-off-by: Anders Roxell <anders.roxell@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: nand: Remove useless line in KconfigMiquel Raynal1-1/+0
Prepare changes that will lay in this file to better express what is NAND related and what is not in menuconfig. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: Clarify Kconfig entry MTD_NANDMiquel Raynal3-5/+5
MTD_NAND is large and encloses much more than what the symbol is actually used for: raw NAND. Clarify the symbol by naming it MTD_RAW_NAND instead. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: rawnand: Change Kconfig titles and re-order a bit the listMiquel Raynal2-177/+181
This list is a mess, while some items should probably not be in the raw/ sub-directory, others are definitely at the right place but not with the right description. Write uniform titles and group IPs by vendor. NAND controllers will appear under the list named "Raw/parallel NAND flash controllers" while the other drivers will appear under "Misc". Software ECC engines will later be moved out of the raw/ directory. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: nand: Clarify Kconfig entry for software Hamming ECC entriesMiquel Raynal6-23/+21
The software Hamming ECC correction implementation is referred as MTD_NAND_ECC which is too generic. Rename it MTD_NAND_ECC_SW_HAMMING. Also rename MTD_NAND_ECC_SMC which is an SMC quirk in the Hamming implementation as MTD_NAND_ECC_SW_HAMMING_SMC. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-18mtd: nand: Clarify Kconfig entry for software BCH ECC algorithmMiquel Raynal5-12/+7
There is no point in having two distinct entries, merge them and rename the symbol for more clarity: MTD_NAND_ECC_SW_BCH Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-08drivers: Remove explicit invocations of mmiowb()Will Deacon2-3/+0
mmiowb() is now implied by spin_unlock() on architectures that require it, so there is no reason to call it from driver code. This patch was generated using coccinelle: @mmiowb@ @@ - mmiowb(); and invoked as: $ for d in drivers include/linux/qed sound; do \ spatch --include-headers --sp-file mmiowb.cocci --dir $d --in-place; done NOTE: mmiowb() has only ever guaranteed ordering in conjunction with spin_unlock(). However, pairing each mmiowb() removal in this patch with the corresponding call to spin_unlock() is not at all trivial, so there is a small chance that this change may regress any drivers incorrectly relying on mmiowb() to order MMIO writes between CPUs using lock-free synchronisation. If you've ended up bisecting to this commit, you can reintroduce the mmiowb() calls using wmb() instead, which should restore the old behaviour on all architectures other than some esoteric ia64 systems. Acked-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
2019-04-08mtd: rawnand: Get rid of chip->ecc_{strength,step}_dsBoris Brezillon14-77/+81
nand_device embeds a nand_ecc_req object which contains the minimum strength and step-size required by the NAND device. Drop the chip->ecc_{strength,step}_ds fields and use chip->base.eccreq.{strength,step_size} instead. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-04-08mtd: rawnand: Get rid of chip->numchipsBoris Brezillon8-25/+17
The same information is provided by nanddev_ntargets(). Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-04-08mtd: rawnand: Get rid of chip->chipsizeBoris Brezillon12-34/+38
The target size can now be returned by nanddev_get_targetsize(). Get rid of the chip->chipsize field and use this helper instead. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-08mtd: rawnand: Get rid of chip->bits_per_cellBoris Brezillon5-8/+2
Now that we inherit from nand_device, we can use nand_device->memorg.bits_per_cell instead of having our own field at the nand_chip level. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-04-08mtd: rawnand: Use nanddev_mtd_max_bad_blocks()Boris Brezillon2-40/+1
nanddev_mtd_max_bad_blocks() is implemented by the generic NAND layer and is already doing what we need. Reuse this function instead of having our own implementation. While at it, get rid of the ->max_bb_per_die and ->blocks_per_die fields which are now unused. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-04-08mtd: rawnand: Move all page cache related fields to a sub-structBoris Brezillon1-14/+14
Looking at the field names it's hard to tell what ->data_buf, ->pagebuf and ->pagebuf_bitflips are for. Clarify that by moving those fields in a sub-struct named pagecache. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-04-08mtd: rawnand: Provide a helper to get chip->data_bufBoris Brezillon7-49/+35
We plan to move cache related fields to a pagecache struct in nand_chip but some drivers access ->pagebuf directly to invalidate the cache before they start using ->data_buf. Let's provide an helper that returns a pointer to ->data_buf after invalidating the cache. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-04-08mtd: rawnand: Initialize the nand_device objectBoris Brezillon2-7/+59
In order to use some of the nanddev_xxx() helpers, we need to initialize the nand_device object embedded in nand_chip using nanddev_init(). This requires implementing nand_ops. We also drop useless mtd->xxx initialization when they're already taken case of by nanddev_init(). Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-04-08mtd: rawnand: Fill memorg during detectionBoris Brezillon11-44/+175
If we want to use the generic NAND layer, we need to have the memorg struct appropriately filled. Patch the detection code to fill this struct. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2019-04-08mtd: spinand: Implement mtd->_max_bad_blocksBoris Brezillon1-0/+1
We just have to use nanddev_mtd_max_bad_blocks(). Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
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