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2014-05-07Merge tag 'for-linus-20140507' of git://git.infradead.org/linux-mtdLinus Torvalds1-0/+6
Pull MTD fix from Brian Norris: "A single update for Keystone SoC's, whose NAND controller does not support subpage programming" * tag 'for-linus-20140507' of git://git.infradead.org/linux-mtd: mtd: davinci-nand: disable subpage write for keystone-nand
2014-05-05UBI: avoid workqueue format string leakKees Cook1-1/+1
When building the name for the workqueue thread, make sure a format string cannot leak in from the disk name. Signed-off-by: Kees Cook <keescook@chromium.org> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2014-05-05UBI: fix ubi free PEBs count calculationTanya Brokhman1-0/+3
The ubi->free_count should be updated with every insert/remove to/from the ubi->free list. Signed-off-by: Tanya Brokhman <tlinder@codeaurora.org> Reviewed-by: Dolev Raviv <draviv@codeaurora.org> Acked-by: Richard Weinberger <richard@nod.at> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2014-05-05UBI: fix error path in __wl_get_pebTanya Brokhman1-0/+3
In case of an error (if there are not free PEB's for example), __wl_get_peb will return a negative value. In order to prevent access violation we need to test the returned value prior to using it later on. Signed-off-by: Tatyana Brokhman <tlinder@codeaurora.org> Reviewed-by: Dolev Raviv <draviv@codeaurora.org> Acked-by: Richard Weinberger <richard@nod.at> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2014-04-30mtd: davinci-nand: disable subpage write for keystone-nandMurali Karicheri1-0/+6
Sub page write doesn't work because of hw issue in controller found on Keystone SOCs. AEMIF controller is also used on DaVinci SOCs which don't seems to have any issue. So add "ti,keysone-nand" compatible to nand driver in order to set NAND_NO_SUBPAGE_WRITE option. Cc: Warner Losh <imp@bsdimp.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-18Shiraz has movedViresh Kumar1-2/+2
shiraz.hashim@st.com email-id doesn't exist anymore as he has left the company. Replace ST's id with shiraz.linux.kernel@gmail.com. It also updates .mailmap file to fix address for 'git shortlog'. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Shiraz Hashim <shiraz.linux.kernel@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2014-04-07Merge tag 'for-linus-20140405' of git://git.infradead.org/linux-mtdLinus Torvalds71-603/+2941
Pull MTD updates from Brian Norris: - A few SPI NOR ID definitions - Kill the NAND "max pagesize" restriction - Fix some x16 bus-width NAND support - Add NAND JEDEC parameter page support - DT bindings for NAND ECC - GPMI NAND updates (subpage reads) - More OMAP NAND refactoring - New STMicro SPI NOR driver (now in 40 patches!) - A few other random bugfixes * tag 'for-linus-20140405' of git://git.infradead.org/linux-mtd: (120 commits) Fix index regression in nand_read_subpage mtd: diskonchip: mem resource name is not optional mtd: nand: fix mention to CONFIG_MTD_NAND_ECC_BCH mtd: nand: fix GET/SET_FEATURES address on 16-bit devices mtd: omap2: Use devm_ioremap_resource() mtd: denali_dt: Use devm_ioremap_resource() mtd: devices: elm: update DRIVER_NAME as "omap-elm" mtd: devices: elm: configure parallel channels based on ecc_steps mtd: devices: elm: clean elm_load_syndrome mtd: devices: elm: check for hardware engine's design constraints mtd: st_spi_fsm: Succinctly reorganise .remove() mtd: st_spi_fsm: Allow loop to run at least once before giving up CPU mtd: st_spi_fsm: Correct vendor name spelling issue - missing "M" mtd: st_spi_fsm: Avoid duplicating MTD core code mtd: st_spi_fsm: Remove useless consts from function arguments mtd: st_spi_fsm: Convert ST SPI FSM (NOR) Flash driver to new DT partitions mtd: st_spi_fsm: Move runtime configurable msg sequences into device's struct mtd: st_spi_fsm: Supply the W25Qxxx chip specific configuration call-back mtd: st_spi_fsm: Supply the S25FLxxx chip specific configuration call-back mtd: st_spi_fsm: Supply the MX25xxx chip specific configuration call-back ...
2014-04-05Merge tag 'drivers-3.15' of ↵Linus Torvalds1-22/+0
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver changes from Arnd Bergmann: "These changes are mostly for ARM specific device drivers that either don't have an upstream maintainer, or that had the maintainer ask us to pick up the changes to avoid conflicts. A large chunk of this are clock drivers (bcm281xx, exynos, versatile, shmobile), aside from that, reset controllers for STi as well as a large rework of the Marvell Orion/EBU watchdog driver are notable" * tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits) Revert "dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac." Revert "net: stmmac: Add SOCFPGA glue driver" ARM: shmobile: r8a7791: Fix SCIFA3-5 clocks ARM: STi: Add reset controller support to mach-sti Kconfig drivers: reset: stih416: add softreset controller drivers: reset: stih415: add softreset controller drivers: reset: Reset controller driver for STiH416 drivers: reset: Reset controller driver for STiH415 drivers: reset: STi SoC system configuration reset controller support dts: socfpga: Add sysmgr node so the gmac can use to reference dts: socfpga: Add support for SD/MMC on the SOCFPGA platform reset: Add optional resets and stubs ARM: shmobile: r7s72100: fix bus clock calculation Power: Reset: Generalize qnap-poweroff to work on Synology devices. dts: socfpga: Update clock entry to support multiple parents ARM: socfpga: Update socfpga_defconfig dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac. net: stmmac: Add SOCFPGA glue driver watchdog: orion_wdt: Use %pa to print 'phys_addr_t' drivers: cci: Export CCI PMU revision ...
2014-04-04Fix index regression in nand_read_subpageRon1-3/+2
Commit 7351d3a5dbf42ba3299af71db3296be447bc1516 added an index variable as part of fixing checkpatch warnings, presumably as a tool to make some long lines shorter, however it only set that index in the case of there being no gaps in eccpos for the fragment being read. Which means the later step of filling ecccode from oob_poi will use the wrong indexing into eccpos in that case. This patch restores the behaviour that existed prior to that change. Signed-off-by: Ron Lee <ron@debian.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-04-04Merge tag 'upstream-3.15-rc1' of git://git.infradead.org/linux-ubifsLinus Torvalds6-0/+715
Pull ubifs updates from Artem Bityutskiy: "This pull request includes the 'ubiblock' driver which provides R/O block access to UBI volumes. It is useful for those who want to use squashfs on top of raw flash devices. UBI will provide bit-flip handling and wear-levelling in this case (e.g., if there are other UBI volumes with R/W UBIFS too). The driver is actually pretty small and it is part of the UBI kernel subsystem. Delivered by Ezequiel Garcia, along with a piece of documentation on the MTD web site and the user-space tool for creating and removing block devices" * tag 'upstream-3.15-rc1' of git://git.infradead.org/linux-ubifs: UBI: block: Remove __initdata from ubiblock_param_ops UBI: make UBI_IOCVOLCRBLK take a parameter for future usage UBI: rename block device ioctls UBI: block: Use ENOSYS as return value when CONFIG_UBIBLOCK=n UBI: block: Add CONFIG_BLOCK dependency UBI: block: Use 'u64' for the 64-bit dividend UBI: block: Mark init-only symbol as __initdata UBI: block: do not use term "attach" UBI: R/O block driver on top of UBI volumes
2014-04-01Merge tag 'char-misc-3.15-rc1' of ↵Linus Torvalds2-1/+2
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc driver patches from Greg KH: "Here's the big char/misc driver updates for 3.15-rc1. Lots of various things here, including the new mcb driver subsystem. All of these have been in linux-next for a while" * tag 'char-misc-3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (118 commits) extcon: Move OF helper function to extcon core and change function name extcon: of: Remove unnecessary function call by using the name of device_node extcon: gpio: Use SIMPLE_DEV_PM_OPS macro extcon: palmas: Use SIMPLE_DEV_PM_OPS macro mei: don't use deprecated DEFINE_PCI_DEVICE_TABLE macro mei: amthif: fix checkpatch error mei: client.h fix checkpatch errors mei: use cl_dbg where appropriate mei: fix Unnecessary space after function pointer name mei: report consistently copy_from/to_user failures mei: drop pr_fmt macros mei: make me hw headers private to me hw. mei: fix memory leak of pending write cb objects mei: me: do not reset when less than expected data is received drivers: mcb: Fix build error discovered by 0-day bot cs5535-mfgpt: Simplify dependencies spmi: pm: drop bus-level PM suspend/resume routines spmi: pmic_arb: make selectable on ARCH_QCOM Drivers: hv: vmbus: Increase the limit on the number of pfns we can handle pch_phub: Report error writing MAC back to user ...
2014-03-31mtd: diskonchip: mem resource name is not optionalSasha Levin1-1/+1
Passing a name to request_mem_region() isn't optional and can't just be NULL. Passing NULL causes a NULL ptr deref later in the boot process. Signed-off-by: Sasha Levin <sasha.levin@oracle.com> Tested-by: Alexander Shiyan <shc_work@mail.ru> Cc: <stable@vger.kernel.org> # 3.14 Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-26mtd: nand: fix mention to CONFIG_MTD_NAND_ECC_BCHErico Nunes1-1/+1
Mention to CONFIG_MTD_ECC_BCH in the warning message can be confusing as this doesn't match the exact name of the configuration option. This warning showed up once to me when I was starting to set up BCH. After checking my .config file, it took a moment before realizing it is CONFIG_MTD_NAND_ECC_BCH instead of CONFIG_MTD_ECC_BCH. Signed-off-by: Erico Nunes <nunes.erico@gmail.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-25mtd: omap2: Use devm_ioremap_resource()Jingoo Han1-20/+3
Use devm_ioremap_resource() in order to make the code simpler, and remove redundant return value check of platform_get_resource() because the value is checked by devm_ioremap_resource(). Also, 'unsigned long mem_size' is removed from 'struct omap_nand_info', because the 'mem_size' variable is not necessary anymore. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-25mtd: denali_dt: Use devm_ioremap_resource()Jingoo Han1-31/+8
Use devm_ioremap_resource() in order to make the code simpler, and remove redundant return value check of platform_get_resource_byname() because the value is checked by devm_ioremap_resource(). Signed-off-by: Jingoo Han <jg1.han@samsung.com> Tested-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-25mtd: devices: elm: update DRIVER_NAME as "omap-elm"Pekon Gupta1-1/+3
use "omap-elm" as DRIVER_NAME Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-25mtd: devices: elm: configure parallel channels based on ecc_stepsPekon Gupta1-3/+5
ELM hardware can process up to maximum of 8 hannels in parallel for ECC error detection. Currently the number of channels getting configured for processing is static determined by macro ERROR_VECTOR_MAX. However, the actual number of channels that need to be processed is the ECC step number. This patch just avoids configuring extra unused channels. Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-25mtd: devices: elm: clean elm_load_syndromePekon Gupta1-7/+11
This patch refactors elm_load_syndrome() to make it scalable for newer ECC schemes by removing scheme specific macros (like ECC_BYTES*xx), and instead using ECC control information passed during elm_config. Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-25mtd: devices: elm: check for hardware engine's design constraintsPekon Gupta2-4/+18
ELM hardware engine is used by BCH ecc-schemes for detecting and locating ECC errors. This patch adds the following checks for ELM hardware engine: - ELM internal buffers are of 1K, so it cannot process data with ecc-step-size > 1K. - ELM engine can execute upto maximum of 8 threads in parallel, so in *page-mode* (when complete page is processed in single iteration), ELM cannot support ecc-steps > 8. Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-21UBI: block: Remove __initdata from ubiblock_param_opsRichard Weinberger1-1/+1
You cannot mark these parameters as __initdata. Otherwise the data is gone upon module exit. Fixes: [ 172.045465] BUG: unable to handle kernel paging request at ffffffffa001db38 [ 172.046020] IP: [<ffffffff81067aa4>] destroy_params+0x24/0x50 Signed-off-by: Richard Weinberger <richard@nod.at> Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
2014-03-20Merge branches 'pm-qos', 'pm-domains' and 'pm-drivers'Rafael J. Wysocki1-1/+1
* pm-qos: PM / QoS: Add type to dev_pm_qos_add_ancestor_request() arguments ACPI / LPSS: Support for device latency tolerance PM QoS ACPI / scan: Add bind/unbind callbacks to struct acpi_scan_handler PM / QoS: Introcuce latency tolerance device PM QoS type PM / QoS: Add no_constraints_value field to struct pm_qos_constraints PM / QoS: Rename device resume latency QoS items * pm-domains: PM / domains: Turn latency warning into debug message * pm-drivers: PM: Add pm_runtime_suspend|resume_force functions PM / runtime: Fetch runtime PM callbacks using a macro
2014-03-20mtd: st_spi_fsm: Succinctly reorganise .remove()Lee Jones1-6/+1
Reported-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Allow loop to run at least once before giving up CPULee Jones1-2/+2
Reported-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Correct vendor name spelling issue - missing "M"Lee Jones1-1/+1
Reported-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Avoid duplicating MTD core codeLee Jones1-8/+0
Reported-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Remove useless consts from function argumentsLee Jones1-8/+7
Reported-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> [Brian: tweaked a bit] Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Convert ST SPI FSM (NOR) Flash driver to new DT partitionsLee Jones1-1/+5
The old API expected a "partitions" property provided a phandle to a separate partitions node, which itself contained yet more nodes each representing one partition. The new API rids the requirement for the superfluous intermediary partitions node. This patch provides the added information required for automatic parsing by the core. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Move runtime configurable msg sequences into device's structLee Jones1-32/+32
Until now the dynamically configurable message sequences for read, write and enable 32bit addressing have been global. Brian makes a good point why this should not be the case. If there are ever two FSM's located on the same platform, we could be potentially introducing a race condition on "needlessly shared data". Suggested-by: Brian Norris <computersforpeace@gmail.com> Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Supply the W25Qxxx chip specific configuration call-backLee Jones1-4/+43
Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Supply the S25FLxxx chip specific configuration call-backLee Jones1-6/+260
This patch allows us to prepare some of the message sequences which will be required to talk to the S25FLxxx family of Serial Flash devices. It also allows us to do some required extra operations after any busy wait failures. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Supply the MX25xxx chip specific configuration call-backLee Jones1-1/+81
Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Add the ability to write to FSM's status registerLee Jones1-0/+36
Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Add the ability to read the FSM's statusLee Jones1-0/+24
Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Erase partly or as a whole a Serial Flash deviceLee Jones1-1/+112
When an erase is requested by userspace the MTD framework calls back into the driver to conduct the actual command issue. Here we provide the routines which do exactly that. We can choose to either do an entire chip erase or by sector. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Supply a busy wait for post-write statusLee Jones1-0/+221
When we write data to the Serial Flash chip we'll wait a predetermined period of time before giving up. During that period of time we poll the status register until completion. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Write to Flash via the FSM FIFOLee Jones1-0/+14
When we write data to the FIFO the FSM Controller subsequently writes that data out to the Serial Flash chip. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Add the ability to read from a Serial Flash deviceLee Jones1-0/+98
When a read is issued by userspace the MTD framework calls back into the driver to conduct the actual command issue and data extraction. Here we provide the routines which do exactly that. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Prepare default sequences for read/write/eraseLee Jones1-0/+36
Most chips require a predefined set of FSM message sequences for read, write and erase operations. This patch provides a way to set them up, which it will do so if a chip specific initialisation routine isn't been provided. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Supply the N25Qxxx chip specific configuration call-backLee Jones1-2/+82
In the FSM driver we handle chip differences by providing the possibility of calling back into a chip specific initialisation routine. In this patch we provide one for the N25Qxxx series, which endeavours to setup things like the read, write and erase sequences, as they differ from the default. We also configure 32bit support and the amount of dummy cycles to use. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Supply the N25Qxxx specific read configurationsLee Jones1-0/+91
The N25Qxxx Serial Flash devices required different sequence configurations depending on whether they're running in 24bit (3Byte) or 32bit (4Byte) mode. We provide those here. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Provide the default read/write configurationsLee Jones1-0/+27
Message sequences can vary depending on how many pads (lines) are required to address the chip (mode & dummy), how many data pads (lines) are required to write out to the chip which will determine speed amongst other things which are detailed by the SFDP specification. We are able to use multiple configurations for each chip, but they need to me matched to a device's capabilities. These configurations are listed in preference order - most preferred first. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Update the flash Volatile Configuration RegisterLee Jones1-0/+32
The FSM Serial Flash Controller is driven by issuing a standard set of register writes we call a message sequence. This patch supplies a method to prepare the message sequence responsible for updating a chip's VCR. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Provide a method to put the chip into 32bit addressing modeLee Jones1-0/+19
Most Serial Flash chips support 24bit addressing as a default but more recent incarnations can support 32bit. Based on information provided though platform specific data and capabilities we can determine whether or not our current chip can. This patch provides a means to setup the FSM message sequence to put the chip into 32bit mode. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Add a check to if the chip can handle an SoC resetLee Jones1-0/+40
Based on information we can obtain though platform specific data and/or chip capabilities we are able to determine whether or not we can handle a SoC reset or not. To find out why this is important please read the comment provided in the patch. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Prepare read/write sequences according to configurationLee Jones1-0/+17
Firstly we search for our preference read/write configuration based on a given chip's capabilities. Then we actually set up the message sequence accordingly. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Provide the sequence for enabling 32bit addressing modeLee Jones1-0/+22
The FSM Serial Flash Controller is driven by issuing a standard set of register writes we call a message sequence. This patch supplies a method to prepare the message sequence responsible for setting 32bit addressing mode on the Flash chip. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Provide the erase one sector sequenceLee Jones1-0/+35
The FSM Serial Flash Controller is driven by issuing a standard set of register writes we call a message sequence. This patch supplies a method to prepare the message sequence responsible for erasing a single sector. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Fetch boot-device from mode pinsLee Jones1-0/+46
It's important for us to determine which device was used to boot from in order to make some correct decisions surrounding Power Management. On each of the platforms which support the FSM this is communicated via a set of mode pins held in the system configuration area. This patch determine the boot device and stores the result. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Prepare the read/write FSM message sequence(s)Lee Jones1-0/+69
The FSM Serial Flash Controller is driven by issuing a standard set of register writes we call a message sequence. This patch supplies a method to prepare read/write FSM message sequence(s) based on chip capability and configuration. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2014-03-20mtd: st_spi_fsm: Use device size to determine address widthLee Jones1-0/+4
Take some known parameters, namely size and number of sectors and use them to determine weather a device can support 32bit addressing or not. If it can, set the associated flash capability flag for latter use. Acked-by Angus Clark <angus.clark@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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