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2020-06-19spi: Move cadence-quadspi driver to drivers/spi/Ramuthevar Vadivel Murugan3-1431/+0
Now that cadence-quadspi has been converted to use spi-mem framework, move it under drivers/spi/ Update license header to match SPI subsystem style Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200601070444.16923-9-vigneshr@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-06-19mtd: spi-nor: Convert cadence-quadspi to use spi-mem frameworkRamuthevar Vadivel Murugan1-285/+191
Move cadence-quadspi driver to use spi-mem framework. This is required to make the driver support for SPI NAND flashes in future. Driver is feature compliant with existing SPI NOR version. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200601070444.16923-8-vigneshr@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-06-19mtd: spi-nor: cadence-quadspi: Drop redundant WREN in erase pathVignesh Raghavendra1-5/+0
Drop redundant WREN command in cqspi_erase() as SPI NOR core takes care of sending WREN command before sending erase command. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200601070444.16923-7-vigneshr@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-06-19mtd: spi-nor: cadence-quadspi: Handle probe deferral while requesting DMA ↵Vignesh Raghavendra1-5/+13
channel dma_request_chan_by_mask() can throw EPROBE_DEFER if DMA provider is not yet probed. Currently driver just falls back to using PIO mode (which is less efficient) in this case. Instead return probe deferral error as is so that driver will be re probed once DMA provider is available. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200601070444.16923-6-vigneshr@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-06-19mtd: spi-nor: cadence-quadspi: Fix error path on failure to acquire reset linesVignesh Raghavendra1-4/+4
Make sure to undo the prior changes done by the driver when exiting due to failure to acquire reset lines. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200601070444.16923-5-vigneshr@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-06-19mtd: spi-nor: cadence-quadspi: Don't initialize rx_dma_complete on failureVignesh Raghavendra1-0/+1
If driver fails to acquire DMA channel then don't initialize rx_dma_complete struct as it won't be used. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200601070444.16923-4-vigneshr@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-06-19mtd: spi-nor: cadence-quadspi: Provide a way to disable DAC modeVignesh Raghavendra1-1/+4
Currently direct access mode is used on platforms that have AHB window (memory mapped window) larger than flash size. This feature is limited to TI platforms as non TI platforms have < 1MB of AHB window. Therefore introduce a driver quirk to disable DAC mode and set it for non TI compatibles. This is in preparation to move to spi-mem framework where flash geometry cannot be known. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200601070444.16923-3-vigneshr@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-06-19mtd: spi-nor: cadence-quadspi: Make driver independent of flash geometryVignesh Raghavendra1-35/+1
Drop configuration of Flash size, erase size and page size configuration. Flash size is needed only if using AHB decoder (BIT 23 of CONFIG_REG) which is not used by the driver. Erase size and page size are needed if IP is configured to send WREN automatically. But since SPI NOR layer takes care of sending WREN, there is no need to configure these fields either. Therefore drop these in preparation to move the driver to spi-mem framework where flash geometry is not visible to controller driver. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200601070444.16923-2-vigneshr@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-05-31mtd: spi-nor: winbond: Fix 4-byte opcode support for w25q256Mantas Pucka3-6/+33
There are 2 different chips (w25q256fv and w25q256jv) that share the same JEDEC ID. Only w25q256jv fully supports 4-byte opcodes. Use SFDP header version to differentiate between them. Fixes: 10050a02f7d5 ("mtd: spi-nor: Add 4B_OPCODES flag to w25q256") Signed-off-by: Mantas Pucka <mantas@8devices.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-05-31mtd: spi-nor: sfdp: add/use local variable in spi_nor_parse_bfpt()Sergei Shtylyov1-11/+11
Despite of how spi_nor_parse_bfpt() abuses the structure fields during their calculation, gcc manages to make some decent code out of that. :-) Yet adding a local variable to store the BFPT DWORDs during calculations still saves 12 bytes of the object code (AArch64 gcc 4.8.5)... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-05-30mtd: spi-nor: sfdp: prepare BFPT parsing for JESD216 rev DPratyush Yadav2-3/+9
JESD216 rev D makes BFPT 20 DWORDs. Update the BFPT size define to reflect that. The check for rev A or later compared the BFPT header length with the maximum BFPT length, BFPT_DWORD_MAX. Since BFPT_DWORD_MAX was 16, and so was the BFPT length for both rev A and B, this check worked fine. But now, since BFPT_DWORD_MAX is 20, it means this check will also stop BFPT parsing for rev A or B, since their length is 16. So, instead check for BFPT_DWORD_MAX_JESD216 to stop BFPT parsing for the first JESD216 version, and check for BFPT_DWORD_MAX_JESD216B for the next two versions. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-05-30mtd: spi-nor: sfdp: default to addr_width of 3 for configurable widthsPratyush Yadav1-0/+1
JESD216D.01 says that when the address width can be 3 or 4, it defaults to 3 and enters 4-byte mode when given the appropriate command. So, when we see a configurable width, default to 3 and let flash that default to 4 change it in a post-bfpt fixup. This fixes SMPT parsing for flashes with configurable address width. If the SMPT descriptor advertises variable address width, we use nor->addr_width as the address width. But since it was not set to any value from the SFDP table, the read command uses an address width of 0, resulting in an incorrect read being issued. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-05-28mtd: spi-nor: Add support for Cypress cy15x104qSascha Hauer1-0/+2
The Cypress cy15b104q and cy15v104q are 4Mbit serial SPI F-RAM devices. Add support for them to the spi-nor driver. The actual Device ID of this chip is 7f 7f 7f 7f 7f 7f c2 2c 04. That is six times the continuation code 7f followed by c2 for Ramtron. Unfortunately the chip sends the Device ID in reversed order, so the continuation code is not at the beginning, but instead at the end. Even more unfortunate is that when reading further the chip sends more 7f codes which means we are not even able to count the continuation codes. We can only hope that this reversed Device ID will never match any other devices ID. Collisions are improbable as of now, the solution from above is good enough. In case of future collisions one can introduce an INFO9 macro, with the downsize that struct flash_info would grow and we have lots of flashes. A more elegant solution would be to introduce dedicated flash ID tables for each bank in JESP106BA. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> [tudor.ambarus@microchip.com: amend commit description with possible future solutions in case collisions occur.] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-05-28mtd: spi-nor: Fix SPI NOR acronymTudor Ambarus6-9/+9
The correct terminology is serial NOR flash or SPI NOR. s/SPI-NOR/SPI NOR and s/spi-nor/SPI NOR across the subsystem. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
2020-05-28mtd: spi-nor: spansion: Differentiate between s25fl256s and s25fs256sTudor Ambarus1-6/+12
s25fs256s was identified as s25fl256s. Differentiate between them by the Family ID using the INFO6 macro. Fixes: b199489d37b2 ("mtd: spi-nor: add the framework for SPI NOR") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
2020-05-28mtd: spi-nor: Add support for s25fs128s1Yicong Yang1-0/+3
Add support for Cypress s25fs128s1 flash. Previously the flash is decoded as s25fl129p1 by mistake. Add it in the flash info list to correctly decode. The flash also needs a fixup for s25fs-s family. Further capability of the flash will be parsed from bfpt. The flash has been tested under SPI/DUAL/QUAD mode on hisi-sfc-v3xx controller, all the write/read/erase works well. Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-05-28mtd: spi-nor: spansion: fix writes on S25FS512SSergei Shtylyov1-2/+23
Spansion S25FS-S family has an issue in the Basic Flash Parameter Table (BFPT): Dword-11 bits 7:4 specify a page size of 512 bytes. Actually this is configurable in the vendor unique register (CR3V) and even the factory default setting is to "wrap at 256 bytes", so blindly relying on BFPT breaks the page writes on these chips. Add the post-BFPT fixup which restores the default page size of 256 bytes -- to properly read CR3V this early is quite intrusive and should better be done as a new feature; Alexander Sverdlin had the patch doing that: https://patchwork.ozlabs.org/project/linux-mtd/patch/20200227123657.26030-1-alexander.sverdlin@nokia.com/ Fixes: dfd2b74530e ("mtd: spi-nor: add Spansion S25FS512S ID") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> Tested-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-04-29mtd: spi-nor: Fix description of the sr_ready() return valueTudor Ambarus1-4/+4
The functions return 1 if ready, 0 if not ready, -errno on errors. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-04-29mtd: spi-nor: Uniformize the return value in spi_nor_*_ready()Tudor Ambarus1-1/+1
spi_nor_ready() returns 1 if ready, 0 if not ready and -errno on errors. Do the same in all the spi_nor_*_ready() children. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-04-29mtd: spi-nor: micron-st: Enable locking for n25q00Jungseung Lee1-0/+2
n25q00 uses the 4 bit Block Protection scheme and supports Top/Bottom protection via the BP and TB bits of the Status Register. Enable locking for n25q00. Tested with cirrus controller. Signed-off-by: Jungseung Lee <js07.lee@samsung.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-04-28mtd: spi-nor: macronix: Add support for mx25u51245gMason Yang1-0/+3
mx25u51245g is a mass production for new design and replace mx66u51235f(phase out). Validated by read, erase, read back, write and read back on Xilinx Zynq PicoZed FPGA board which included Macronix SPI Host (driver/spi/spi-mxic.c). Signed-off-by: Mason Yang <masonccyang@mxic.com.tw> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-04-28mtd: spi-nor: macronix: Add support for mx25l51245gMason Yang1-0/+3
mx25l51245g is a mass production for new design and replace mx66l51235l(phase out). Validated by read, erase, read back, write and read back on Xilinx Zynq PicoZed FPGA board which included Macronix SPI Host (driver/spi/spi-mxic.c). Signed-off-by: Mason Yang <masonccyang@mxic.com.tw> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-04-28mtd: spi-nor: core: fix kernel-doc typo for spi_nor_[{info|sfdp}_]init_params()Sergei Shtylyov1-3/+3
When spi_nor_info_init_params(), spi_nor_sfdp_init_params(), and spi_nor_init_params() were added, the kernel-doc for them contained a typo: 'struct spi-nor' instead of 'struct spi_nor' -- fix them. Fixes: 1c1d8d98e1c7 ("mtd: spi-nor: Split spi_nor_init_params()") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-04-28mtd: spi-nor: core: fix kernel-doc typo for spi_nor_manufacturer_init_params()Sergei Shtylyov1-1/+1
When spi_nor_manufacturer_init_params() was added, the kernel-doc for it contained a typo: 'struct spi-nor' instead of 'struct spi_nor' -- fix it. Fixes: ce0b6f3f3c43 ("mtd: spi-nor: Add default_init() hook to tweak flash parameters") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-04-21mtd: spi-nor: Enable locking for n25q128a11Xiang Chen1-1/+3
As 4bit block protection patchset for some micron models are merged, n25q128a11 also uses 4 bit Block Protection scheme, so enable locking for it. Tested it on n25q128a11, the locking functions work well. Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Reviewed-by: Jungseung Lee <js07.lee@samsung.com> Tested-by: Shreyas Joshi <shreyasjoshi15@gmail.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-04-20mtd: spi-nor: spansion: Enable dual and quad read for s25fl256s0Takahiro Kuwano1-1/+3
The s25fl256s0 supports dual and quad read like s25fl256s1. Enable it by adding SPI_NOR_DUAL_READ and SPI_NOR_QUAD_READ flags to the flash_info entry. Tested with the device and confirmed that is working. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@cypress.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-04-09mtd: spi-nor: Compile files in controllers/ directoryGuenter Roeck1-0/+2
Commit a0900d0195d2 ("mtd: spi-nor: Prepare core / manufacturer code split") moved various files into a new directory, but did not add the new directory to its parent directory Makefile. The moved files no longer build, and affected flash chips no longer instantiate. Adding the new directory to the parent directory Makefile fixes the problem. Fixes: a0900d0195d2 ("mtd: spi-nor: Prepare core / manufacturer code split") Cc: Boris Brezillon <bbrezillon@kernel.org> Cc: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Acked-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Richard Weinberger <richard@nod.at>
2020-03-30mtd: Convert fallthrough comments into statementsMiquel Raynal2-2/+1
Use Joe Perches cvt_fallthrough.pl script to convert /* fallthrough */ comments (and its derivatives) into a fallthrough; statement. This automatically drops useless ones. Do it MTD-wide. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Tudor Ambarus <tudor.ambarus@microchip.com> Acked-by: Richard Weinberger <richard@nod.at> Link: https://lore.kernel.org/linux-mtd/20200325212115.14170-1-miquel.raynal@bootlin.com
2020-03-24mtd: spi-nor: Enable locking for n25q512ax3/n25q512aJungseung Lee1-2/+6
n25q512ax3 and n25q512a use the 4 bit Block Protection scheme. Enable locking for both. Tested on n25q512ax3. The other is modified following the datasheet. Signed-off-by: Jungseung Lee <js07.lee@samsung.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-03-24mtd: spi-nor: Add SR 4bit block protection supportJungseung Lee2-18/+58
Currently we are supporting block protection only for flash chips with 3 block protection bits (BP0-2) in the SR register. Enable block protection support for flashes with 4 block protection bits (BP0-3). Add a flash_info flag for flashes that describe 4 block protection bits. Add another flash_info flag for flashes in which BP3 bit is not adjacent to the BP0-2 bits. Tested with a n25q512ax3 (BP0-3) and w25q128 (BP0-2). Signed-off-by: Jungseung Lee <js07.lee@samsung.com> Reviewed-by: Michael Walle <michael@walle.cc> Tested-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-03-24mtd: spi-nor: Add generic formula for SR block protection handlingJungseung Lee1-31/+41
The current mainline locking was restricted and could only be applied to flashes that have 3 block protection bits and fixed locking ratio. A new method of normalization was reached at the end of the discussion [1]. (1) - if bp slot is insufficient. (2) - if bp slot is sufficient. if (bp_slots_needed > bp_slots) // (1) min_prot_length = sector_size << (bp_slots_needed - bp_slots); else // (2) min_prot_length = sector_size; This patch changes logic to handle block protection based on min_prot_length. It is suitable for the overall flashes with exception of some corner cases (see EON and catalyst) and easy to extend and apply for the case of 2bit or 4bit block protection. [1] http://lists.infradead.org/pipermail/linux-mtd/2020-February/093934.html Signed-off-by: Jungseung Lee <js07.lee@samsung.com> Reviewed-by: Michael Walle <michael@walle.cc> Tested-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-03-24mtd: spi-nor: Set all BP bits to one when lock_len == mtd->sizeTudor Ambarus1-7/+13
When there are more BP settings than needed for defining the protected areas of the flash memory, most flashes will define the remaining settings as "protect all", i.e. the equivalent of having all the BP bits set to one. But there are flashes where the in-between BP values are undefined (not mentioned), and only the "all bits set" is protecting the entire memory. One such example is w25q80, where BP[2:0]=0b101 and 0b110 are not defined. Set all the BP bits to one when lock_len == mtd->size, to treat this special case. Suggested-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Jungseung Lee <js07.lee@samsung.com> Reviewed-by: Michael Walle <michael@walle.cc>
2020-03-23mtd: spi-nor: controllers: aspeed-smc: Replace zero-length array with ↵Gustavo A. R. Silva1-1/+1
flexible-array member The current codebase makes use of the zero-length array language extension to the C90 standard, but the preferred mechanism to declare variable-length types such as these ones is a flexible array member[1][2], introduced in C99: struct foo { int stuff; struct boo array[]; }; By making use of the mechanism above, we will get a compiler warning in case the flexible array does not occur last in the structure, which will help us prevent some kind of undefined behavior bugs from being inadvertently introduced[3] to the codebase from now on. Also, notice that, dynamic memory allocations won't be affected by this change: "Flexible array members have incomplete type, and so the sizeof operator may not be applied. As a quirk of the original implementation of zero-length arrays, sizeof evaluates to zero."[1] This issue was found with the help of Coccinelle. [1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html [2] https://github.com/KSPP/linux/issues/21 [3] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour") Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-03-23mtd: spi-nor: Clear WEL bit when erase or program errors occurTudor Ambarus1-0/+22
When an Erase or Program error occurs on a spansion/cypress or a micron flash, the WEL bit remains set to one and should be cleared with a WRDI command in order to protect against inadvertent writes that can possible corrupt the contents of the memory. Winbond, macronix, gd, etc., do not support the E_ERR and P_ERR bits in the Status Register and always clear the WEL bit regardless of the outcome of the erase or page program operation (ex w25q40bw, MX25L25635E). Issue a WRDI command when erase or page program errors occur. Reported-by: John Garry <john.garry@huawei.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: John Garry <john.garry@huawei.com>
2020-03-17mtd: spi-nor: Trim what is exposed in spi-nor.hTudor Ambarus10-42/+288
The SPI NOR controllers drivers must not be able to use structures that are meant just for the SPI NOR core. struct spi_nor_flash_parameter is filled at run-time with info gathered from flash_info, manufacturer and sfdp data. struct spi_nor_flash_parameter should be opaque to the SPI NOR controller drivers, make sure it is. spi_nor_option_flags, spi_nor_read_command, spi_nor_pp_command, spi_nor_read_command_index and spi_nor_pp_command_index are defined for the core use, make sure they are opaque to the SPI NOR controller drivers. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-03-17mtd: spi-nor: Drop the MFR definitionsTudor Ambarus1-2/+0
Cross manufacturer code is unlikely and discouraged, get rid of the MFR definitions. Suggested-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
2020-03-17mtd: spi-nor: Get rid of the now empty spi_nor_ids[] tableBoris Brezillon1-25/+0
All entries have been moved to manufacturer drivers. Get rid of this empty table. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-03-17mtd: spi-nor: Move XMC bits out of core.cBoris Brezillon4-3/+26
Create a SPI NOR manufacturer driver for XMC chips, and move the XMC definitions outside of core.c. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-03-17mtd: spi-nor: Move Xilinx bits out of core.cBoris Brezillon4-86/+98
Create a SPI NOR manufacturer driver for Xilinx chips, and move the Xilinx definitions outside of core.c. While at it, remove the SPI_S3AN flag which is now useless. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-03-17mtd: spi-nor: Move Catalyst bits out of core.cBoris Brezillon4-7/+32
Create a SPI NOR manufacturer driver for Catalyst chips, and move the Catalyst definitions outside of core.c. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-03-17mtd: spi-nor: Move Winbond bits out of core.cBoris Brezillon4-114/+115
Create a SPI NOR manufacturer driver for Winbond chips, and move the Winbond definitions outside of core.c. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-03-17mtd: spi-nor: Move SST bits out of core.cBoris Brezillon4-120/+156
Create a SPI NOR manufacturer driver for SST chips, and move the SST definitions outside of core.c. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-03-17mtd: spi-nor: Move Spansion bits out of core.cBoris Brezillon4-58/+98
Create a SPI NOR manufacturer driver for Spansion chips, and move the Spansion definitions outside of core.c. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-03-17mtd: spi-nor: Move Micron/ST bits out of core.cBoris Brezillon4-120/+158
Create a SPI NOR manufacturer driver for Micron/ST chips, and move the Micron/ST definitions outside of core.c. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-03-17mtd: spi-nor: Move Macronix bits out of core.cBoris Brezillon4-68/+101
Create a SPI NOR manufacturer driver for Macronix chips, and move the Macronix definitions outside of core.c. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Xiang Chen <chenxiang66@hisilicon.com>
2020-03-17mtd: spi-nor: Move ISSI bits out of core.cBoris Brezillon4-65/+86
Create a SPI NOR manufacturer driver for ISSI chips, and move the ISSI definitions outside of core.c. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-03-17mtd: spi-nor: Move Intel bits out of core.cBoris Brezillon4-14/+35
Create a SPI NOR manufacturer driver for Intel chips, and move the Intel definitions outside of core.c. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2020-03-17mtd: spi-nor: Move GigaDevice bits out of core.cBoris Brezillon4-59/+62
Create a SPI NOR manufacturer driver for GigaDevice chips, and move the GigaDevice definitions outside of core.c. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-03-17mtd: spi-nor: Move Fujitsu bits out of core.cBoris Brezillon4-3/+23
Create a SPI NOR manufacturer driver for Fujitsu chips, and move the Fujitsu definitions outside of core.c. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2020-03-17mtd: spi-nor: Move Everspin bits out of core.cBoris Brezillon4-6/+30
Create a SPI NOR manufacturer driver for Everspin chips, and move the Everspin definitions outside of core.c. Signed-off-by: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
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