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path: root/drivers/mmc/host/sdhci-tegra.c
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2021-12-14mmc: sdhci-tegra: Fix switch to HS400ES modePrathamesh Shete1-17/+26
When CMD13 is sent after switching to HS400ES mode, the bus is operating at either MMC_HIGH_26_MAX_DTR or MMC_HIGH_52_MAX_DTR. To meet Tegra SDHCI requirement at HS400ES mode, force SDHCI interface clock to MMC_HS200_MAX_DTR (200 MHz) so that host controller CAR clock and the interface clock are rate matched. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Fixes: dfc9700cef77 ("mmc: tegra: Implement HS400 enhanced strobe") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20211214113653.4631-1-pshete@nvidia.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-08-24mmc: sdhci-tegra: Enable MMC_CAP2_ALT_GPT_TEGRADmitry Osipenko1-0/+9
Tegra20/30/114/124 Android devices place GPT at a non-standard location. Enable GPT entry scanning at that location. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20210820004536.15791-5-digetx@gmail.com Signed-off-by: Jens Axboe <axboe@kernel.dk>
2021-04-12mmc: sdhci-tegra: Add required callbacks to set/clear CQE_EN bitAniruddha Tvs Rao1-0/+32
CMD8 is not supported with Command Queue Enabled. Add required callback to clear CQE_EN and CQE_INTR fields in the host controller register before sending CMD8. Add corresponding callback in the CQHCI resume path to re-enable CQE_EN and CQE_INTR fields. Reported-by: Kamal Mostafa <kamal@canonical.com> Tested-by: Kamal Mostafa <kamal@canonical.com> Signed-off-by: Aniruddha Tvs Rao <anrao@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210407094617.770495-1-jonathanh@nvidia.com Cc: stable@vger.kernel.org # v5.10+ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-03-30mmc: sdhci: replace mmc->parent with mmc_dev() for consistencyJisheng Zhang1-17/+17
As pointed out by Ulf, "both "mmc->parent" and mmc_dev(mmc) are being used in the entire c-file". Convert all the mmc->parent usage in all sdhci host driver to mmc_dev() for consistency. Suggested-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Link: https://lore.kernel.org/r/20210324155013.1e5faa3c@xhacker.debian Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-17mmc: sdhci: tegra: fix wrong unit with busy_timeoutWolfram Sang1-1/+1
'busy_timeout' is in msecs, not in jiffies. Use the correct factor. Fixes: 5e958e4aacf4 ("sdhci: tegra: Implement Tegra specific set_timeout callback") Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20201116132206.23518-1-wsa+renesas@sang-engineering.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-09-07mmc: Set PROBE_PREFER_ASYNCHRONOUS for drivers that existed in v4.4Douglas Anderson1-0/+1
This is like commit 3d3451124f3d ("mmc: sdhci-msm: Prefer asynchronous probe") but applied to a whole pile of drivers. This batch converts the drivers that appeared to be around in the v4.4 timeframe. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> # SH_MMCIF Tested-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200903162412.1.Id501e96fa63224f77bb86b2135a5e8324ffb9c43@changeid Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-09-07mmc: sdhci-tegra: Simplify with dev_err_probe()Krzysztof Kozlowski1-5/+2
Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200902193658.20539-9-krzk@kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-08-28sdhci: tegra: Add missing TMCLK for data timeoutSowjanya Komatineni1-2/+51
commit b5a84ecf025a ("mmc: tegra: Add Tegra210 support") Tegra210 and later has a separate sdmmc_legacy_tm (TMCLK) used by Tegra SDMMC hawdware for data timeout to achive better timeout than using SDCLK and using TMCLK is recommended. USE_TMCLK_FOR_DATA_TIMEOUT bit in Tegra SDMMC register SDHCI_TEGRA_VENDOR_SYS_SW_CTRL can be used to choose either TMCLK or SDCLK for data timeout. Default USE_TMCLK_FOR_DATA_TIMEOUT bit is set to 1 and TMCLK is used for data timeout by Tegra SDMMC hardware and having TMCLK not enabled is not recommended. So, this patch adds quirk NVQUIRK_HAS_TMCLK for SoC having separate timeout clock and keeps TMCLK enabled all the time. Fixes: b5a84ecf025a ("mmc: tegra: Add Tegra210 support") Cc: stable <stable@vger.kernel.org> # 5.4 Tested-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1598548861-32373-8-git-send-email-skomatineni@nvidia.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-08-28sdhci: tegra: Remove SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK for Tegra186Sowjanya Komatineni1-1/+0
commit 4346b7c7941d ("mmc: tegra: Add Tegra186 support") SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK is set for Tegra186 from the beginning of its support in driver. Tegra186 SDMMC hardware by default uses timeout clock (TMCLK) instead of SDCLK and this quirk should not be set. So, this patch remove this quirk for Tegra186. Fixes: 4346b7c7941d ("mmc: tegra: Add Tegra186 support") Cc: stable <stable@vger.kernel.org> # 5.4 Tested-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1598548861-32373-3-git-send-email-skomatineni@nvidia.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-08-28sdhci: tegra: Remove SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK for Tegra210Sowjanya Komatineni1-1/+0
commit b5a84ecf025a ("mmc: tegra: Add Tegra210 support") SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK is set for Tegra210 from the beginning of Tegra210 support in the driver. Tegra210 SDMMC hardware by default uses timeout clock (TMCLK) instead of SDCLK and this quirk should not be set. So, this patch remove this quirk for Tegra210. Fixes: b5a84ecf025a ("mmc: tegra: Add Tegra210 support") Cc: stable <stable@vger.kernel.org> # 5.4 Tested-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1598548861-32373-2-git-send-email-skomatineni@nvidia.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-07-13mmc: sdhci-tegra: Add comment for PADCALIB and PAD_CONTROL NVQUIRKSSowjanya Komatineni1-0/+9
This patch adds comments about NVQUIRKS HAS_PADCALIB and NEEDS_PAD_CONTROL. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1591326240-28928-1-git-send-email-skomatineni@nvidia.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-05-28sdhci: tegra: Avoid reading autocal timeout values when not applicableSowjanya Komatineni1-24/+33
When auto calibration timeouts, calibration is disabled and fail-safe drive strength values are programmed based on the signal voltage. Different fail-safe drive strength values based on voltage are applicable only for SoCs supporting 3V3 and 1V8 pad controls. So, this patch avoids reading these properties from the device tree for SoCs not using pad controls and the warning of missing properties will not show up on these SoC platforms. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1590005337-1087-1-git-send-email-skomatineni@nvidia.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-03-24sdhci: tegra: Enable MMC_CAP_WAIT_WHILE_BUSY host capabilitySowjanya Komatineni1-2/+2
Tegra sdhci host supports HW busy detection of the device busy signaling over data0 lane. So, this patch enables host capability MMC_CAP_wAIT_WHILE_BUSY. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1583941675-9884-2-git-send-email-skomatineni@nvidia.com [Ulf: Lumped together the caps assignments] Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-03-24sdhci: tegra: Implement Tegra specific set_timeout callbackSowjanya Komatineni1-0/+31
Tegra host supports HW busy detection and timeouts based on the count programmed in SDHCI_TIMEOUT_CONTROL register and max busy timeout it supports is 11s in finite busy wait mode. Some operations like SLEEP_AWAKE, ERASE and flush cache through SWITCH commands take longer than 11s and Tegra host supports infinite HW busy wait mode where HW waits forever till the card is busy without HW timeout. This patch implements Tegra specific set_timeout sdhci_ops to allow switching between finite and infinite HW busy detection wait modes based on the device command expected operation time. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/1583941675-9884-1-git-send-email-skomatineni@nvidia.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-03-11mmc: sdhci-tegra: Fix busy detection by enabling MMC_CAP_NEED_RSP_BUSYUlf Hansson1-0/+3
It has turned out that the sdhci-tegra controller requires the R1B response, for commands that has this response associated with them. So, converting from an R1B to an R1 response for a CMD6 for example, leads to problems with the HW busy detection support. Fix this by informing the mmc core about the requirement, via setting the host cap, MMC_CAP_NEED_RSP_BUSY. Reported-by: Bitan Biswas <bbiswas@nvidia.com> Reported-by: Peter Geis <pgwipeout@gmail.com> Suggested-by: Sowjanya Komatineni <skomatineni@nvidia.com> Cc: <stable@vger.kernel.org> Tested-by: Sowjanya Komatineni <skomatineni@nvidia.com> Tested-By: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-01-16mmc: tegra: fix SDR50 tuning overrideMichał Mirosław1-1/+1
Commit 7ad2ed1dfcbe inadvertently mixed up a quirk flag's name and broke SDR50 tuning override. Use correct NVQUIRK_ name. Fixes: 7ad2ed1dfcbe ("mmc: tegra: enable UHS-I modes") Cc: <stable@vger.kernel.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Link: https://lore.kernel.org/r/9aff1d859935e59edd81e4939e40d6c55e0b55f6.1578390388.git.mirq-linux@rere.qmqm.pl Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-27mmc: tegra: Implement ->set_dma_mask()Nicolin Chen1-20/+28
The SDHCI controller on Tegra186 supports 40-bit addressing, which is usually enough to address all of system memory. However, if the SDHCI controller is behind an IOMMU, the address space can go beyond. This happens on Tegra186 and later where the ARM SMMU has an input address space of 48 bits. If the DMA API is backed by this ARM SMMU, the top- down IOVA allocator will cause IOV addresses to be returned that the SDHCI controller cannot access. Unfortunately, prior to the introduction of the ->set_dma_mask() host operation, the SDHCI core would set either a 64-bit DMA mask if the controller claimed to support 64-bit addressing, or a 32-bit DMA mask otherwise. Since the full 64 bits cannot be addressed on Tegra, this had to be worked around in commit 68481a7e1c84 ("mmc: tegra: Mark 64 bit dma broken on Tegra186") by setting the SDHCI_QUIRK2_BROKEN_64_BIT_DMA quirk, which effectively restricts the DMA mask to 32 bits. One disadvantage of this is that dma_map_*() APIs will now try to use the swiotlb to bounce DMA to addresses beyond of the controller's DMA mask. This in turn caused degraded performance and can lead to situations where the swiotlb buffer is exhausted, which in turn leads to DMA transfers to fail. With the recent introduction of the ->set_dma_mask() host operation, this can now be properly fixed. For each generation of Tegra, the exact supported DMA mask can be configured. This kills two birds with one stone: it avoids the use of bounce buffers because system memory never exceeds the addressable memory range of the SDHCI controllers on these devices, and at the same time when an IOMMU is involved, it prevents IOV addresses from being allocated beyond the addressible range of the controllers. Since the DMA mask is now properly handled, the 64-bit DMA quirk can be removed. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> [treding@nvidia.com: provide more background in commit message] Tested-by: Nicolin Chen <nicoleotsuka@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Cc: stable@vger.kernel.org # v4.15 + Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-08-21Revert "mmc: sdhci-tegra: drop ->get_ro() implementation"Dmitry Osipenko1-0/+14
The WRITE_PROTECT bit is always in a "protected mode" on Tegra and WP-GPIO state need to be used instead. In a case of the GPIO absence, write-enable should be assumed. External SD is writable once again as a result of this patch because the offending commit changed behaviour for the case of a missing WP-GPIO to fall back to WRITE_PROTECT bit-checking, which is incorrect for Tegra. Cc: stable@vger.kernel.org # v5.1+ Fixes: e8391453e27f ("mmc: sdhci-tegra: drop ->get_ro() implementation") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-06-10sdhci: tegra: Do not log error message on deferred probeThierry Reding1-1/+4
Recent changes have made it much more likely that clocks are not available, when the SDHCI driver is first probed. However, that is a situation that the driver can cope with just fine. To avoid confusion, don't output an error when this happens. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-06-08Merge tag 'spdx-5.2-rc4' of ↵Linus Torvalds1-10/+1
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull yet more SPDX updates from Greg KH: "Another round of SPDX header file fixes for 5.2-rc4 These are all more "GPL-2.0-or-later" or "GPL-2.0-only" tags being added, based on the text in the files. We are slowly chipping away at the 700+ different ways people tried to write the license text. All of these were reviewed on the spdx mailing list by a number of different people. We now have over 60% of the kernel files covered with SPDX tags: $ ./scripts/spdxcheck.py -v 2>&1 | grep Files Files checked: 64533 Files with SPDX: 40392 Files with errors: 0 I think the majority of the "easy" fixups are now done, it's now the start of the longer-tail of crazy variants to wade through" * tag 'spdx-5.2-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (159 commits) treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 450 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 449 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 448 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 446 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 445 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 444 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 443 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 442 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 441 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 440 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 438 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 437 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 436 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 435 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 434 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 433 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 432 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 431 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 430 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 429 ...
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282Thomas Gleixner1-10/+1
Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 285 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-28mmc: tegra: Fix a warning messageDan Carpenter1-1/+1
The WARN_ON() macro takes a condition, not a warning message. I've changed this to use WARN(1, "msg... Fixes: ea8fc5953e8b ("mmc: tegra: update hw tuning process") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-04-15mmc: tegra: add sdhci tegra suspend and resumeSowjanya Komatineni1-1/+57
This patch adds suspend and resume PM ops for tegra SDHCI. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-04-15mmc: tegra: fix CQE enable and resume sequenceSowjanya Komatineni1-10/+62
Tegra CQHCI/SDHCI design prevents write access to SDHCI block size register when CQE is enabled and unhalted. CQHCI driver enables CQE prior to invoking sdhci_cqe_enable which violates this Tegra specific host requirement. This patch fixes this by configuring sdhci block registers prior to CQE unhalt. This patch also has a fix for retry of unhalt due to known Tegra specific CQE resume bug where first unhalt might not succeed when clear all tasks is performed prior to resume and need a second unhalt. This patch also includes CQE enable fix for CMD CRC errors that happen with the specific sandisk emmc device when status command is sent during the transfer of last data block due to marginal timing. Tested-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-04-15mmc: tegra: add Tegra186 WAR for CQESowjanya Komatineni1-1/+16
Tegra186 CQHCI host has a known bug where CQHCI controller selects DATA_PRESENT_SELECT bit to 1 for DCMDs with R1B response type and since DCMD does not trigger any data transfer, DCMD task complete happens leaving the DATA FSM of host controller in wait state for the data. This effects the data transfer tasks issued after the DCMDs with R1b response type resulting in timeout. SW WAR is to set CMD_TIMING to 1 in DCMD task descriptor. This bug and SW WAR is applicable only for Tegra186 and not for Tegra194. This patch implements this WAR thru NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING for Tegra186 and also implements update_dcmd_desc of cqhci_host_ops interface to set CMD_TIMING bit depending on the NVQUIRK. Tested-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-04-15mmc: tegra: update hw tuning processSowjanya Komatineni1-1/+215
This patch includes below HW tuning related fixes. configures tuning parameters as per Tegra TRM WAR fix for manual tap change HW auto-tuning post process As per Tegra TRM, SDR50 mode tuning execution takes upto maximum of 256 tuning iterations and SDR104/HS200/HS400 modes tuning execution takes upto maximum of 128 tuning iterations. This patch programs tuning control register with maximum tuning iterations needed based on the timing along with the start tap, multiplier, and step size used by the HW tuning. Tegra210 has a known issue of glitch on trimmer output when the tap value is changed with the trimmer input clock running and the WAR is to disable card clock before sending tuning command and after sending tuning command wait for 1usec and issue SW reset followed by enabling card clock. This WAR is applicable when changing tap value manually as well. Tegra SDHCI driver has this implemented correctly for manual tap change but missing SW reset before enabling card clock during sending tuning command. Issuing SW reset during tuning command as a part of WAR and is applicable in cases where tuning is performed with single step size for more iterations. This patch includes this fix. HW auto-tuning finds the best largest passing window and sets the tap at the middle of the window. With some devices like sandisk eMMC driving fast edges and due to high tap to tap delay in the Tegra chipset, auto-tuning does not detect falling tap between the valid windows resulting in a parital window or a merged window and the best tap is set at the signal transition which is actually the worst tap location. Recommended SW solution is to detect if the best passing window picked by the HW tuning is a partial or a merged window based on min and max tap delays found from chip characterization across PVT and perform tuning correction to pick the best tap. This patch has implementation of this post HW tuning process for the tegra hosts that support HW tuning through the callback function tegra_sdhci_execute_hw_tuning and uses the tuned tap delay. Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-04-15mmc: tegra: fix ddr signaling for non-ddr modesSowjanya Komatineni1-0/+1
ddr_signaling is set to true for DDR50 and DDR52 modes but is not set back to false for other modes. This programs incorrect host clock when mode change happens from DDR52/DDR50 to other SDR or HS modes like incase of mmc_retune where it switches from HS400 to HS DDR and then from HS DDR to HS mode and then to HS200. This patch fixes the ddr_signaling to set properly for non DDR modes. Tested-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Cc: stable@vger.kernel.org # v4.20 + Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: sdhci-tegra: drop ->get_ro() implementationThomas Petazzoni1-9/+0
The SDHCI core is know properly checking for the state of a WP GPIO, so there is no longer any need for the sdhci-tegra code to implement ->get_ro() using mmc_gpio_get_ro(). Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: tegra: HW Command Queue Support for Tegra SDMMCSowjanya Komatineni1-4/+113
This patch adds HW Command Queue for supported Tegra SDMMC controllers. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-25mmc: tegra: SDMMC pads auto-calibrationSowjanya Komatineni1-41/+119
Program initial drive code offsets which will be used by auto calibration process. Program fixed drive strengths for SDMMC pads in pad control register when auto cal timeouts. Fixed settings are based on Pre-SI analysis of the pad design. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: tegra: Fix for SDMMC pads autocal parsing from dtSowjanya Komatineni1-4/+4
Some of the SDMMC pads auto calibration values parsed from devicetree are assigned incorrectly. This patch fixes it. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Thierry Reding <treding@nvidia.com> Fixes: 51b77c8ea784 ("mmc: tegra: Program pad autocal offsets from dt") Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: fix inconsistent IS_ERR and PTR_ERRYueHaibing1-1/+1
Fix inconsistent IS_ERR and PTR_ERR in tegra_sdhci_init_pinctrl_info, the proper pointer to be passed as argument is 'pinctrl_state_1v8' Signed-off-by: YueHaibing <yuehaibing@huawei.com> Reviewed-by: Aapo Vienamo <aapo.vienamo@iki.fi> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Implement periodic pad calibrationAapo Vienamo1-0/+22
Rerun the pad calibration procedure before sdhci_request() if the 100 ms recalibration interval has been exceeded. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Implement HS400 delay line calibrationAapo Vienamo1-0/+29
Implement HS400 specific delay line calibration procedure. This is a Tegra specific procedure and has to be performed regardless whether enhanced strobe or HS400 tuning is used. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Implement HS400 enhanced strobeAapo Vienamo1-0/+23
Implement eMMC HS400 enhanced strobe. Enhanced strobe is an alternative mechanism to the HS400 tuning procedure. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Parse and program DQS trim valueAapo Vienamo1-3/+29
Parse and program the HS400 DQS trim value from DT. Program a fallback value in case the property is missing. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Enable UHS and HS200 modes for Tegra186Aapo Vienamo1-1/+3
Set nvquirks to enable higher speed modes. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Enable UHS and HS200 modes for Tegra210Aapo Vienamo1-1/+3
Set nvquirks to enable higher speed modes. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Disable card clock during tuning cmd on Tegra210Aapo Vienamo1-23/+58
Implement tegra210_sdhci_writew() to disable card clock and issue a reset when the tuning command is sent. This is done to prevent an intermittent hang with around 10 % failure rate during tuning. Add tegra186_sdhci_ops because this workaround is specific to Tegra210. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Remove tegra_sdhci_writew() from tegra210_sdhci_opsAapo Vienamo1-1/+0
tegra_sdhci_writew() defers the write to SDHCI_TRANSFER_MODE until SDHCI_COMMAND is written. This is not necessary on Tegra210 and Tegra186 and it breaks read-modify-write operations on SDHCI_TRANSFER_MODE because writes to SDHCI_TRANSFER_MODE aren't visible until SDHCI_COMMAND has been written to. This results in tuning failures on Tegra210. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Use standard SDHCI tuning on Tegra210 and Tegra186Aapo Vienamo1-2/+15
Add a new sdhci_ops struct for Tegra210 and Tegra186 which doesn't set the custom tuning callback used on previous SoC generations. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Configure default trim value on resetAapo Vienamo1-1/+6
Program the outbound sampling trim value in tegra_sdhci_reset(). Unlike the outbound tap value this does not depend on the signaling mode and needs to be only programmed once. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Configure default tap valuesAapo Vienamo1-55/+77
Set the default inbound timing adjustment tap value on reset and on non-tunable modes. The default tap value is not programmed on tunable modes because the tuning sequence is used instead to determine the tap value. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Parse default trim and tap from dtAapo Vienamo1-0/+22
Parse the default inbound and outbound sampling trimmer values from the device tree. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Add a workaround for tap value change glitchAapo Vienamo1-2/+28
Add quirk to disable the card clock during configuration of the tap value in tegra_sdhci_set_tap() and issue sdhci_reset() after value change. This is a workaround to avoid propagation of a potential glitch caused by setting the tap value. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Enable pad calibration on Tegra210 and Tegra186Aapo Vienamo1-2/+4
Set NVQUIRK_HAS_PADCALIB on Tegra210 and Tegra186 to enable automatic pad drive strength calibration. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Perform pad calibration after voltage switchAapo Vienamo1-0/+5
Run the automatic pad calibration after voltage switching if tegra_host->pad_calib_required is set. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Program pad autocal offsets from dtAapo Vienamo1-1/+151
Parse the pad drive strength calibration offsets from the device tree. Program the calibration offsets in accordance with the current signaling mode. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Disable card clock during pad calibrationAapo Vienamo1-0/+26
Disable the card clock during automatic pad drive strength calibration and re-enable it afterwards. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-10-08mmc: tegra: Power on the calibration padAapo Vienamo1-0/+26
Automatic pad drive strength calibration is performed on a separate pad identical to the ones used for driving the actual bus. Power on the calibration pad during the calibration procedure and power it off afterwards to save power. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-16 21:36:08 +0000