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path: root/drivers/mmc/host/sdhci-pci-gli.c
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2021-06-14mmc: sdhci-pci-gli: Fine tune GL9763E L1 entry delayBen Chuang1-2/+2
Fine tune the value to 21us in order to improve read/write performance. Signed-off-by: Ben Chuang <benchuanggli@gmail.com> Link: https://lore.kernel.org/r/20210511061835.5559-1-benchuanggli@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-05-10mmc: sdhci-pci-gli: increase 1.8V regulator waitDaniel Beer1-1/+6
Inserting an SD-card on an Intel NUC10i3FNK4 (which contains a GL9755) results in the message: mmc0: 1.8V regulator output did not become stable Following this message, some cards work (sometimes), but most cards fail with EILSEQ. This behaviour is observed on Debian 10 running kernel 4.19.188, but also with 5.8.18 and 5.11.15. The driver currently waits 5ms after switching on the 1.8V regulator for it to become stable. Increasing this to 10ms gets rid of the warning about stability, but most cards still fail. Increasing it to 20ms gets some cards working (a 32GB Samsung micro SD works, a 128GB ADATA doesn't). At 50ms, the ADATA works most of the time, and at 100ms both cards work reliably. Signed-off-by: Daniel Beer <dlbeer@gmail.com> Acked-by: Ben Chuang <benchuanggli@gmail.com> Fixes: e51df6ce668a ("mmc: host: sdhci-pci: Add Genesys Logic GL975x support") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20210424081652.GA16047@nyquist.nev Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-04-15mmc: sdhci-pci-gli: Enlarge ASPM L1 entry delay of GL975xBen Chuang1-0/+32
GL975x enters ASPM L1 state after a short idle in default. Enlarge the idle period to 7.9us for improving the R/W performance. Signed-off-by: Ben Chuang <benchuanggli@gmail.com> Link: https://lore.kernel.org/r/20210415032637.5219-1-benchuanggli@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-04-12mmc: sdhci-pci-gli: Improve GL9763E L1 entry delay to increase battery lifeBen Chuang1-3/+3
For GL9763E, although there is the best performance at the maximum delay. Change the value to 20us in order to have better power consumption. This change may reduce the maximum performance by 10%. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Link: https://lore.kernel.org/r/20210407093816.8863-1-benchuanggli@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-03-30mmc: sdhci-pci-gli: Enable short circuit protection mechanism of GL9755Renius Chen1-0/+8
Short circuit protection mechanism of GL9755 is disabled by HW default setting. Enable short circuit protection to prevent GL9755 from being damaged by short circuit or over current. Signed-off-by: Renius Chen <reniuschengl@gmail.com> Link: https://lore.kernel.org/r/20210225111307.62975-1-reniuschengl@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: sdhci-pci-gli: Finetune HS400 RX delay for GL9763ERenius Chen1-0/+9
To improve the compatibility of GL9763E with HS400 eMMC cards, finetune the RX delay of HS400 mode. Signed-off-by: Renius Chen <reniuschengl@gmail.com> Link: https://lore.kernel.org/r/20210111082249.17092-1-reniuschengl@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: sdhci-pci-gli: Enlarge ASPM L1 entry delay of GL9763ERenius Chen1-0/+10
GL9763E enters ASPM L1 state after a very short idle in default, even during a burst of request. So the R/W performance of GL9763E is low with some platforms, which support ASPM mechanism, due to entering ASPM L1 state very frequently in R/W process. Set the L1 entry delay bits in vendor-specific register to 0x3FF to enlarge the idle period to 260us for improving the R/W performance of GL9763E. Signed-off-by: Renius Chen <reniuschengl@gmail.com> Link: https://lore.kernel.org/r/20210115054736.27769-1-reniuschengl@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2021-02-01mmc: sdhci-pci-gli: Add a switch to enable/disable CQHCI supportRenius Chen1-1/+3
Add a vendor-specific bit named GLI_9763E_MB_ERP_ON at the bit7 of register 888h to decide whether to enhance random R/W performance of GL9763E. CQHCI support will be enabled if and only if the bit is set and the GLI_9763E_MB_CMQ_OFF bit is not set. Signed-off-by: Renius Chen <reniuschengl@gmail.com> Link: https://lore.kernel.org/r/20210106085332.5494-1-reniuschengl@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-12-04mmc: sdhci-pci-gli: Disable slow mode in HS400 mode for GL9763EBen Chuang1-0/+7
The GL9763E uses 150Mhz (slow mode) by default in HS400 mode. In order to make HS400 mode run at 200Mhz, the slow mode needs to be turned off. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Link: https://lore.kernel.org/r/20201125110145.2824-1-benchuanggli@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-11-24mmc: sdhci-pci-gli: Reduce power consumption for GL9755Ben Chuang1-0/+20
For GL9755, reduce power consumption by lowering the LFCLK and disabling the DMACLK on low-power. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Link: https://lore.kernel.org/r/20201123053702.6083-1-benchuanggli@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-10-07mmc: sdhci-pci-gli: Add CQHCI Support for GL9763EBen Chuang1-2/+148
Add CQHCI initialization and implement CQHCI operations for GL9763E. Use bit19 of the register (0x888) to decide whether to disable command queuing. If the bit is set, the command queuing will be disabled. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Link: https://lore.kernel.org/r/20201005105509.11343-1-ben.chuanggli@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-07-24mmc: sdhci-pci-gli: Set SDR104's clock to 205MHz and enable SSC for GL975xBen Chuang1-2/+218
Set SDR104's clock to 205MHz and enable SSC for GL9750 and GL9755 Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Link: https://lore.kernel.org/r/20200717033350.13006-1-benchuanggli@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-05-28mmc: sdhci-pci-gli: Add Genesys Logic GL9763E supportBen Chuang1-0/+106
GL9763E supports High Speed SDR, High Speed DDR, HS200, HS400, Enhanced Strobe in HS400 mode, 1/4/8 bits data bus and 3.3/1.8V. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Link: https://lore.kernel.org/r/20200508064154.13473-1-benchuanggli@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-05-07mmc: sdhci-pci-gli: Fix can not access GL9750 after reboot from Windows 10Ben Chuang1-0/+5
Need to clear some bits in a vendor-defined register after reboot from Windows 10. Fixes: e51df6ce668a ("mmc: host: sdhci-pci: Add Genesys Logic GL975x support") Reported-by: Grzegorz Kowal <custos.mentis@gmail.com> Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Tested-by: Grzegorz Kowal <custos.mentis@gmail.com> Link: https://lore.kernel.org/r/20200504063957.6638-1-benchuanggli@gmail.com Cc: stable@vger.kernel.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-05-07mmc: sdhci-pci-gli: Fix no irq handler from suspendBen Chuang1-0/+18
The kernel prints a message similar to "[ 28.881959] do_IRQ: 5.36 No irq handler for vector" when GL975x resumes from suspend. Implement a resume callback to fix this. Fixes: 31e43f31890c ("mmc: sdhci-pci-gli: Enable MSI interrupt for GL975x") Co-developed-by: Renius Chen <renius.chen@genesyslogic.com.tw> Signed-off-by: Renius Chen <renius.chen@genesyslogic.com.tw> Tested-by: Dave Flogeras <dflogeras2@gmail.com> Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Tested-by: Vineeth Pillai <vineethrp@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/20200427103048.20785-1-benchuanggli@gmail.com Cc: stable@vger.kernel.org Signed-off-by: Samuel Zou <zou_wei@huawei.com> [Samuel Zou: Make sdhci_pci_gli_resume() static] Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2020-03-04mmc: sdhci-pci-gli: Enable MSI interrupt for GL975xBen Chuang1-0/+17
Enable MSI interrupt for GL9750/GL9755. Some platforms do not support PCI INTx and devices can not work without interrupt. Like messages below: [ 4.487132] sdhci-pci 0000:01:00.0: SDHCI controller found [17a0:9755] (rev 0) [ 4.487198] ACPI BIOS Error (bug): Could not resolve symbol [\_SB.PCI0.PBR2._PRT.APS2], AE_NOT_FOUND (20190816/psargs-330) [ 4.487397] ACPI Error: Aborting method \_SB.PCI0.PBR2._PRT due to previous error (AE_NOT_FOUND) (20190816/psparse-529) [ 4.487707] pcieport 0000:00:01.3: can't derive routing for PCI INT A [ 4.487709] sdhci-pci 0000:01:00.0: PCI INT A: no GSI Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Tested-by: Raul E Rangel <rrangel@chromium.org> Fixes: e51df6ce668a ("mmc: host: sdhci-pci: Add Genesys Logic GL975x support") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200219092900.9151-1-benchuanggli@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-09-27mmc: host: sdhci-pci: Add Genesys Logic GL975x supportBen Chuang1-0/+352
Add support for the GL9750 and GL9755 chipsets. Enable v4 mode and wait 5ms after set 1.8V signal enable for GL9750/ GL9755. Fix the value of SDHCI_MAX_CURRENT register and use the vendor tuning flow for GL9750. Co-developed-by: Michael K Johnson <johnsonm@danlj.org> Signed-off-by: Michael K Johnson <johnsonm@danlj.org> Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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