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linux
WIP-syscall
master
mmu_gather-race-fix
n900-dt
n900-dt-with-ssi
n900-dts-twl5030
n900-modem-rework
n900-omapdrm
next
proc-cmdline
sc18is600
ssi
ssi-cleaned
ssi-cleaned-dt
ssi-cleaned-dt2
ssi-cleaned-dt3
tty-splice
twl4030-madc-cleanup
Linux Kernel (branches are rebased on master from time to time)
Linus Torvalds
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drivers
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media
Age
Commit message (
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Author
Files
Lines
2020-12-15
Merge tag 'net-next-5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/ne...
Linus Torvalds
1
-0
/
+1
2020-12-14
Merge tag 'media/v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mc...
Linus Torvalds
238
-7944
/
+23754
2020-12-14
Merge tag 'drm-next-2020-12-11' of git://anongit.freedesktop.org/drm/drm
Linus Torvalds
3
-17
/
+40
2020-12-11
Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
Jakub Kicinski
7
-32
/
+58
2020-12-08
media: vidtv: fix some warnings
Mauro Carvalho Chehab
3
-3
/
+5
2020-12-07
media: ccs: Add support for obtaining C-PHY configuration from firmware
Sakari Ailus
1
-0
/
+4
2020-12-07
media: ccs-pll: Print pixel rates
Sakari Ailus
1
-0
/
+5
2020-12-07
media: ccs: Print written register values
Sakari Ailus
1
-0
/
+4
2020-12-07
media: ccs: Add support for DDR OP SYS and OP PIX clocks
Sakari Ailus
1
-1
/
+8
2020-12-07
media: ccs-pll: Add support for DDR OP system and pixel clocks
Sakari Ailus
2
-20
/
+46
2020-12-07
media: ccs: Dual PLL support
Sakari Ailus
2
-3
/
+51
2020-12-07
media: ccs-pll: Add trivial dual PLL support
Sakari Ailus
2
-22
/
+196
2020-12-07
media: ccs-pll: Separate VT divisor limit calculation from the rest
Sakari Ailus
1
-27
/
+37
2020-12-07
media: ccs-pll: Fix VT post-PLL divisor calculation
Sakari Ailus
1
-5
/
+7
2020-12-07
media: ccs-pll: Make VT divisors 16-bit
Sakari Ailus
1
-26
/
+25
2020-12-07
media: ccs-pll: Rework bounds checks
Sakari Ailus
2
-57
/
+95
2020-12-07
media: ccs-pll: Print relevant information on PLL tree
Sakari Ailus
1
-19
/
+66
2020-12-07
media: ccs-pll: Better separate OP and VT sub-tree calculation
Sakari Ailus
1
-23
/
+31
2020-12-07
media: ccs-pll: Check for derating and overrating, support non-derating sensors
Sakari Ailus
3
-29
/
+64
2020-12-07
media: ccs-pll: Split off VT subtree calculation
Sakari Ailus
1
-124
/
+131
2020-12-07
media: ccs-pll: Add C-PHY support
Sakari Ailus
1
-9
/
+26
2020-12-07
media: ccs-pll: Add sanity checks
Sakari Ailus
1
-0
/
+9
2020-12-07
media: ccs-pll: Add support flexible OP PLL pixel clock divider
Sakari Ailus
3
-8
/
+23
2020-12-07
media: ccs-pll: Support two cycles per pixel on OP domain
Sakari Ailus
3
-6
/
+16
2020-12-07
media: ccs-pll: Add support for extended input PLL clock divider
Sakari Ailus
3
-1
/
+7
2020-12-07
media: ccs-pll: Add support for decoupled OP domain calculation
Sakari Ailus
4
-19
/
+23
2020-12-07
media: ccs: Add support for lane speed model
Sakari Ailus
1
-1
/
+10
2020-12-07
media: ccs-pll: Add support for lane speed model
Sakari Ailus
2
-11
/
+31
2020-12-07
media: ccs-pll: Use explicit 32-bit unsigned type
Sakari Ailus
1
-2
/
+2
2020-12-07
media: ccs-pll: Fix check for PLL multiplier upper bound
Sakari Ailus
1
-2
/
+1
2020-12-07
media: ccs-pll: Fix comment on check against maximum PLL multiplier
Sakari Ailus
1
-1
/
+1
2020-12-07
media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound search
Sakari Ailus
1
-2
/
+9
2020-12-07
media: ccs-pll: Fix condition for pre-PLL divider lower bound
Sakari Ailus
1
-1
/
+1
2020-12-07
media: ccs-pll: Begin calculation from OP system clock frequency
Sakari Ailus
1
-8
/
+4
2020-12-07
media: ccs-pll: Use the BIT macro
Sakari Ailus
1
-2
/
+5
2020-12-07
media: ccs-pll: Document the structs in the header as well as the function
Sakari Ailus
1
-0
/
+89
2020-12-07
media: ccs-pll: Move the flags field down, away from 8-bit fields
Sakari Ailus
1
-1
/
+1
2020-12-07
media: ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY
Sakari Ailus
3
-3
/
+4
2020-12-07
media: ccs-pll: Remove parallel bus support
Sakari Ailus
2
-15
/
+4
2020-12-07
media: ccs-pll: End search if there are no better values available
Sakari Ailus
1
-2
/
+8
2020-12-07
media: ccs-pll: Use correct VT divisor for calculating VT SYS divisor
Sakari Ailus
1
-2
/
+2
2020-12-07
media: ccs-pll: Split limits and PLL configuration into front and back parts
Sakari Ailus
3
-188
/
+209
2020-12-07
media: ccs-pll: Don't use div_u64 to divide a 32-bit number
Sakari Ailus
1
-1
/
+1
2020-12-07
media: vivid: fix 'disconnect' error injection
Hans Verkuil
3
-30
/
+66
2020-12-07
media: rcar-vin: Mask VNCSI_IFMD register
Jacopo Mondi
1
-3
/
+22
2020-12-07
media: meson: Add M2M driver for the Amlogic GE2D Accelerator Unit
Neil Armstrong
5
-0
/
+1445
2020-12-07
media: gspca: Fix memory leak in probe
Alan Stern
1
-0
/
+1
2020-12-07
media: ccs: Fix return value from probe
Sakari Ailus
1
-1
/
+1
2020-12-07
media: ccs: avoid printing an uninitialized variable
Arnd Bergmann
1
-2
/
+1
2020-12-07
media: i2c: fix an uninitialized error code
Arnd Bergmann
1
-1
/
+3
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