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path: root/drivers/media/platform/cadence
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2018-06-27media: v4l: cadence: add VIDEO_V4L2 dependencyArnd Bergmann1-0/+2
The cadence media drivers can be built-in while the v4l2 core is a loadable module. This is a mistake and leads to link errors: drivers/media/v4l2-core/v4l2-fwnode.o: In function `v4l2_async_register_subdev_sensor_common': v4l2-fwnode.c:(.text+0x12f0): undefined reference to `v4l2_async_subdev_notifier_register' v4l2-fwnode.c:(.text+0x1304): undefined reference to `v4l2_async_register_subdev' v4l2-fwnode.c:(.text+0x1318): undefined reference to `v4l2_async_notifier_unregister' v4l2-fwnode.c:(.text+0x1338): undefined reference to `v4l2_async_notifier_cleanup' cdns-csi2rx.c:(.text+0x9f8): undefined reference to `v4l2_subdev_init' cdns-csi2rx.c:(.text+0xa78): undefined reference to `v4l2_async_register_subdev' drivers/media/platform/cadence/cdns-csi2tx.o: In function `csi2tx_remove': cdns-csi2tx.c:(.text+0x88): undefined reference to `v4l2_async_unregister_subdev' drivers/media/platform/cadence/cdns-csi2tx.o: In function `csi2tx_probe': cdns-csi2tx.c:(.text+0x884): undefined reference to `v4l2_subdev_init' cdns-csi2tx.c:(.text+0xa9c): undefined reference to `v4l2_async_register_subdev' An explicit Kconfig dependency on VIDEO_V4L2 avoids the problem. Fixes: 1fc3b37f34f6 ("media: v4l: cadence: Add Cadence MIPI-CSI2 RX driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
2018-06-27media: v4l: cadence: include linux/slab.hArnd Bergmann2-0/+2
I ran into a randconfig build error with the new driver: drivers/media/platform/cadence/cdns-csi2tx.c: In function 'csi2tx_probe': drivers/media/platform/cadence/cdns-csi2tx.c:477:11: error: implicit declaration of function 'kzalloc'; did you mean 'd_alloc'? [-Werror=implicit-function-declaration] kzalloc() is declared in linux/slab.h, so let's include this to make it build in all configurations. Fixes: 84b477e6d4bc ("media: v4l: cadence: Add Cadence MIPI-CSI2 TX driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
2018-05-17media: v4l: cadence: Add Cadence MIPI-CSI2 TX driverMaxime Ripard3-0/+575
The Cadence MIPI-CSI2 TX controller is an hardware block meant to be used as a bridge between pixel interfaces and a CSI-2 bus. It supports operating with an internal or external D-PHY, with up to 4 lanes, or without any D-PHY. The current code only supports the latter case. While the virtual channel input on the pixel interface can be directly mapped to CSI2, the datatype input is actually a selection signal (3-bits) mapping to a table of up to 8 preconfigured datatypes/formats (programmed at start-up) The block supports up to 8 input datatypes. Acked-by: Benoit Parrot <bparrot@ti.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
2018-05-17media: cadence: csi2rx: Fix csi2rx_start error handlingSakari Ailus1-2/+2
The clocks enabled by csi2rx_start function are intended to be disabled in an error path but there are two issues: 1) the loop condition is always true and 2) the first clock disabled is the the one enabling of which failed. Fix these two bugs by changing the loop condition as well as only disabling the clocks that were actually enabled. Reported-by: Mauro Chehab <mchehab@kernel.org> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
2018-05-16media: v4l: cadence: Add Cadence MIPI-CSI2 RX driverMaxime Ripard3-0/+524
The Cadence CSI-2 RX Controller is an hardware block meant to be used as a bridge between a CSI-2 bus and pixel grabbers. It supports operating with internal or external D-PHY, with up to 4 lanes, or without any D-PHY. The current code only supports the latter case. It also support dynamic mapping of the CSI-2 virtual channels to the associated pixel grabbers, but that isn't allowed at the moment either. Acked-by: Benoit Parrot <bparrot@ti.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>