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2021-08-31mailbox: cmdq: add multi-gce clocks support for mt8195jason-jh.lin1-22/+79
For the design of GCE hardware event signal transportation, evnet rx will send the event signal to all GCE event merges after receiving the event signal from the other hardware. Because GCE event merges need to response to event rx, their clocks must be enabled at that time. To make sure all the gce clock is enabled while receiving the hardware event, each cmdq mailbox should enable or disable the others gce clk at the same time. Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-08-31mailbox: cmdq: add mediatek mailbox support for mt8195jason-jh.lin1-0/+1
Add mt8195 compatible name in the driver data of cmdq mailbox driver. Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-08-30mailbox: qcom-apcs-ipc: Add compatible for MSM8953 SoCVladimir Lypak1-0/+1
MSM8953 has an APCS block similar to MSM8916 but with different clocks which are spread over 2MB IO region next to it. Signed-off-by: Vladimir Lypak <junak.pub@gmail.com> Signed-off-by: Sireesh Kodali <sireeshkodali@protonmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-08-30mailbox: qcom: Add support for SM6115 APCS IPCIskren Chernev1-0/+1
Qcom SM4250/6115, have APCS mailbox setup similar to msm8998 and msm8916. Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-08-30soc: mediatek: cmdq: add address shift in jumpYongqiang Niu1-1/+2
Add address shift when compose jump instruction to compatible with 35bit format. Fixes: 0858fde496f8 ("mailbox: cmdq: variablize address shift in platform") Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-08-30mailbox: cmdq: add mt8192 supportYongqiang Niu1-0/+10
add mt8192 support Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-08-29mailbox: qcom-ipcc: Enable loading QCOM_IPCC as a moduleAmit Pundir2-1/+2
This patch enables the qcom_ipcc driver to be loaded as a module. IPCC is fairly core to system, so as such it should never be unloaded. It registers as a mailbox + irq controller and the irq controller drivers in kernel are not supposed to be unloaded as they don't have the visibility over the clients consuming the irqs. Hence adding supress_bind_attrs to disable bind/unbind via sysfs. Signed-off-by: Amit Pundir <amit.pundir@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-08-29mailbox: sti: quieten kernel-doc warningsRandy Dunlap1-8/+8
Use kernel-doc struct notation for the mailbox structs to prevent these kernel-doc warnings: drivers/mailbox/mailbox-sti.c:39: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * STi Mailbox device data drivers/mailbox/mailbox-sti.c:63: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * STi Mailbox platform specific configuration drivers/mailbox/mailbox-sti.c:74: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * STi Mailbox allocated channel information Also move the field descriptions ahead of the function description as is expected in kernel-doc. This prevents another kernel-doc warning. Fixes: 9ef4546cbd7e ("mailbox: Add support for ST's Mailbox IP") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: kernel test robot <lkp@intel.com> Cc: Aditya Srivastava <yashsri421@gmail.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mbox: add polarfire soc system controller mailboxConor Dooley3-0/+265
This driver adds support for the single mailbox channel of the MSS system controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: imx: Avoid using val uninitialized in imx_mu_isr()Nathan Chancellor1-1/+3
Clang warns: drivers/mailbox/imx-mailbox.c:284:2: warning: variable 'val' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized] default: ^~~~~~~ drivers/mailbox/imx-mailbox.c:288:7: note: uninitialized use occurs here if (!val) ^~~ drivers/mailbox/imx-mailbox.c:263:9: note: initialize the variable 'val' to silence this warning u32 val, ctrl; ^ = 0 1 warning generated. Prior to commit 91c8c1fbe498 ("mailbox: imx: add xSR/xCR register array"), val was always initialized in imx_mu_isr() but now, it is not initialized in the default case. Return IRQ_NONE like the statement below does and add a message that there is an unhandled type for this switch statement so that it can be updated. Fixes: 91c8c1fbe498 ("mailbox: imx: add xSR/xCR register array") Link: https://github.com/ClangBuiltLinux/linux/issues/1404 Signed-off-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: qcom: Add MSM8939 APCS supportShawn Guo1-0/+1
Enable MSM8939 APCS support by adding the compatible. It reuses msm8916_apcs_data. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: qcom: Use PLATFORM_DEVID_AUTO to register platform deviceShawn Guo1-1/+1
In adding APCS clock support for MSM8939, the second clock registration fails due to duplicate device name like below. [ 0.519657] sysfs: cannot create duplicate filename '/bus/platform/devices/qcom-apcs-msm8916-clk' ... [ 0.661158] qcom_apcs_ipc b111000.mailbox: failed to register APCS clk This is because MSM8939 has 3 APCS instances for Cluster0 (little cores), Cluster1 (big cores) and CCI (Cache Coherent Interconnect). Although only APCS of Cluster0 and Cluster1 have IPC bits, each of 3 APCS has A53PLL clock control bits. That said, 3 'qcom-apcs-msm8916-clk' devices need to be registered to instantiate all 3 clocks. Use PLATFORM_DEVID_AUTO rather than PLATFORM_DEVID_NONE for platform_device_register_data() call to fix the issue above. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: qcom-apcs: Add SM6125 compatibleMartin Botka1-0/+5
This commit adds compatible for the SM6125 SoC Signed-off-by: Martin Botka <martin.botka@somainline.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: mtk-cmdq: Fix uninitialized variable in cmdq_mbox_flush()Dan Carpenter1-1/+1
The "cb" pointer needs to be initialized before can assign "data.data = cb->data;". Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: bcm-flexrm-mailbox: Remove redundant dev_err call in ↵Zhihao Cheng1-1/+0
flexrm_mbox_probe() There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zhihao Cheng <chengzhihao1@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: bcm2835: Remove redundant dev_err call in bcm2835_mbox_probe()Zhihao Cheng1-1/+0
There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zhihao Cheng <chengzhihao1@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: qcom-ipcc: Fix IPCC mbox channel exhaustionSibi Sankar1-0/+6
Fix IPCC (Inter-Processor Communication Controller) channel exhaustion by setting the channel private data to NULL on mbox shutdown. Err Logs: remoteproc: MBA booted without debug policy, loading mpss remoteproc: glink-edge: failed to acquire IPC channel remoteproc: failed to probe subdevices for remoteproc: -16 Fixes: fa74a0257f45 ("mailbox: Add support for Qualcomm IPCC") Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Cc: stable@vger.kernel.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: mtk-cmdq: Add struct cmdq_pkt in struct cmdq_cb_dataChun-Kuang Hu1-0/+2
Current client use 'struct cmdq_pkt' as callback data, so change 'void *data' to 'struct cmdq_pkt *pkt'. Keep data until client use pkt instead of data. Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: mtk-cmdq: Use mailbox rx_callbackChun-Kuang Hu1-5/+9
rx_callback is a standard mailbox callback mechanism and could cover the function of proprietary cmdq_task_cb, so use the standard one instead of the proprietary one. But the client driver has already used cmdq_task_cb, so keep cmdq_task_cb until all client driver use rx_callback instead of cmdq_task_cb. Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: mtk-cmdq: Remove cmdq_cb_statusChun-Kuang Hu1-5/+5
cmdq_cb_status is an error status. Use the standard error number instead of cmdq_cb_status to prevent status duplication. Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: imx-mailbox: support i.MX8ULP MUPeng Fan1-41/+63
i.MX8ULP MU has different register layout and bit layout compared with i.MX6SX/7ULP/8. So add enum imx_mu_type to show it is IMX_MU_V2 or IMX_MU_V1. For IMX_MU_V2 mu hardware, check it when calculating bit offset to get the correct offset. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: imx: add xSR/xCR register arrayPeng Fan1-35/+61
We are going to add a new platform which has 4 status registers(SR, TSR, RSR, GSR) and 4 control registers(CR, TCR, RCR, GCR), so extend xSR and xCR to register array and adapt code to use it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: imx: replace the xTR/xRR array with single registerPeng Fan1-14/+14
The xTR/xRR registers are using 4 bytes stride and continuous. Considering we will support more TR and RR registers, use base + idx * 4 method to calculate register address, not hardcoding in driver. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: hisilicon: Use the correct HiSilicon copyrightHao Fang2-2/+2
s/Hisilicon/HiSilicon/. It should use capital S, according to https://www.hisilicon.com/en. Signed-off-by: Hao Fang <fanghao11@huawei.com> Reviewed-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: mediatek: Remove redundant error printing in cmdq_probe()Zhen Lei1-3/+1
When devm_ioremap_resource() fails, a clear enough error message will be printed by its subfunction __devm_ioremap_resource(). The error information contains the device name, failure cause, and possibly resource information. Therefore, remove the error printing here to simplify code and reduce the binary size. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: bcm-pdc: Remove redundant error printing in pdc_probe()Zhen Lei1-1/+0
When devm_ioremap_resource() fails, a clear enough error message will be printed by its subfunction __devm_ioremap_resource(). The error information contains the device name, failure cause, and possibly resource information. Therefore, remove the error printing here to simplify code and reduce the binary size. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-06-26mailbox: arm_mhu: Remove redundant error printing in mhu_probe()Zhen Lei1-3/+1
When devm_ioremap_resource() fails, a clear enough error message will be printed by its subfunction __devm_ioremap_resource(). The error information contains the device name, failure cause, and possibly resource information. Therefore, remove the error printing here to simplify code and reduce the binary size. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-04-28Merge tag 'mailbox-v5.13' of ↵Linus Torvalds9-53/+119
git://git.linaro.org/landing-teams/working/fujitsu/integration Pull mailbox updates from Jassi Brar: "qcom: - enable support for SM8350 and SC7280 sprd: - refcount channel usage - specify interrupt names in dt - support sc9863a arm: - drop redundant print ti: - convert dt-bindings to json schema and misc spelling fixes" * tag 'mailbox-v5.13' of git://git.linaro.org/landing-teams/working/fujitsu/integration: dt-bindings: mailbox: qcom-ipcc: Add compatible for SC7280 dt-bindings: mailbox: ti,secure-proxy: Convert to json schema mailbox: arm_mhu_db: Remove redundant dev_err call in mhu_db_probe() mailbox: sprd: Add supplementary inbox support dt-bindings: mailbox: Add interrupt-names to SPRD mailbox mailbox: sprd: Introduce refcnt when clients requests/free channels MAINTAINERS: Add DT bindings directory to mailbox mailbox: fix various typos in comments mailbox: pcc: fix platform_no_drv_owner.cocci warnings dt-bindings: mailbox: Add compatible for SM8350 IPCC
2021-04-13mailbox: arm_mhu_db: Remove redundant dev_err call in mhu_db_probe()Qiheng Lin1-3/+1
There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Qiheng Lin <linqiheng@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-04-13mailbox: sprd: Add supplementary inbox supportOrson Zhai1-17/+71
Some sensors connected to Unisoc mailbox will send data very frequently. This makes channel 0 very busy and the messages from other remote cores not able to be handled as soon as possible. It's a trick (un-documented) from Unisoc ASIC designers to resolve this special requirement that an inbox assigned to one of the remote cores before was modified to be exposed to host cpu core. Then from host side, a supplementary inbox is added for transferring mass but not emergency messages from the remote cores, such as step counting sensor, with an independent FIFO and interrupt which is as same as channel 0. Meanwihle, inbox part of this channel is still kept for original remote core to use. Signed-off-by: Orson Zhai <orson.zhai@unisoc.com> Reviewed-by: Baolin Wang <baolin.wang7@gmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-04-13mailbox: sprd: Introduce refcnt when clients requests/free channelsOrson Zhai1-14/+29
Unisoc mailbox has no way to be enabled/disabled for any single channel. They can only be set to startup or shutdown as a whole device at same time. Add a variable to count references to avoid mailbox FIFO being reset unexpectedly when clients are requesting or freeing channels. Also add a lock to dismiss possible conflicts from register r/w in different startup or shutdown threads. And fix the crash problem when early interrupts come from channel which has not been requested by client yet. Fixes: ca27fc26cd22 ("mailbox: sprd: Add Spreadtrum mailbox driver") Signed-off-by: Orson Zhai <orson.zhai@unisoc.com> Reviewed-by: Baolin Wang <baolin.wang7@gmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-04-13mailbox: fix various typos in commentsTom Saeger8-16/+16
Fix trivial typos in mailbox driver comments. s/Intergrated/Integrated/ s/extenstion/extension/ s/atleast/at least/ s/commnunication/communication/ s/assgined/assigned/ s/commnunication/communication/ s/recevied/received/ s/succeded/succeeded/ s/implmentation/implementation/ s/definiation/definition/ s/traget/target/ s/wont/won't/ Cc: trivial@kernel.org Signed-off-by: Tom Saeger <tom.saeger@oracle.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-04-13mailbox: pcc: fix platform_no_drv_owner.cocci warningsYang Li1-1/+0
./drivers/mailbox/pcc.c:580:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-04-09treewide: change my e-mail address, fix my nameMarek Behún1-2/+2
Change my e-mail address to kabel@kernel.org, and fix my name in non-code parts (add diacritical mark). Link: https://lkml.kernel.org/r/20210325171123.28093-2-kabel@kernel.org Signed-off-by: Marek Behún <kabel@kernel.org> Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jassi Brar <jassisinghbrar@gmail.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Pavel Machek <pavel@ucw.cz> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2021-02-22mailbox: arm_mhuv2: Skip calling kfree() with invalid pointerViresh Kumar1-1/+3
It is possible that 'data' passed to kfree() is set to a error value instead of allocated space. Make sure it doesn't get called with invalid pointer. Fixes: 5a6338cce9f4 ("mailbox: arm_mhuv2: Add driver") Cc: v5.11 <stable@vger.kernel.org> # v5.11 Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-02-14mailbox: tegra-hsp: Set lockdep class dynamicallyMikko Perttunen1-0/+15
On Tegra194, due to both BPMP and TCU using mailboxes, we get a lockdep spew at boot. Both are using different instances of HSP, so this is harmless. As such give each HSP instance a different lockdep class. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-02-14mailbox: sprd: correct definition of SPRD_OUTBOX_FIFO_FULLMagnum Shan1-1/+1
According to the specification, bit[2] represents SPRD_OUTBOX_FIFO_FULL, not bit[0], so correct it. Fixes: ca27fc26cd22 ("mailbox: sprd: Add Spreadtrum mailbox driver") Signed-off-by: Magnum Shan <magnum.shan@unisoc.com> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Reviewed-by: Baolin Wang <baolin.wang7@gmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-02-14mailbox: arm_mhuv2: make remove callback return voidUwe Kleine-König1-3/+1
My build tests failed to catch that amba driver that would have needed adaption in commit 3fd269e74f2f ("amba: Make the remove callback return void"). Change the remove function to make the driver build again. Reported-by: kernel test robot <lkp@intel.com> Fixes: 3fd269e74f2f ("amba: Make the remove callback return void") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-02-14mailbox: arm_mhuv2: Fix sparse warningsViresh Kumar1-11/+11
This patch fixes a bunch of sparse warnings in the newly added arm_mhuv2 driver. drivers/mailbox/arm_mhuv2.c:506:24: warning: incorrect type in argument 1 (different address spaces) drivers/mailbox/arm_mhuv2.c:506:24: expected void const volatile [noderef] __iomem *addr drivers/mailbox/arm_mhuv2.c:506:24: got unsigned int [usertype] * drivers/mailbox/arm_mhuv2.c:547:42: warning: incorrect type in argument 2 (different address spaces) drivers/mailbox/arm_mhuv2.c:547:42: expected unsigned int [usertype] *reg drivers/mailbox/arm_mhuv2.c:547:42: got unsigned int [noderef] __iomem * drivers/mailbox/arm_mhuv2.c:625:42: warning: incorrect type in argument 2 (different address spaces) drivers/mailbox/arm_mhuv2.c:625:42: expected unsigned int [usertype] *reg drivers/mailbox/arm_mhuv2.c:625:42: got unsigned int [noderef] __iomem * drivers/mailbox/arm_mhuv2.c:972:24: warning: dereference of noderef expression drivers/mailbox/arm_mhuv2.c:973:22: warning: dereference of noderef expression drivers/mailbox/arm_mhuv2.c:993:25: warning: dereference of noderef expression drivers/mailbox/arm_mhuv2.c:1026:24: warning: dereference of noderef expression drivers/mailbox/arm_mhuv2.c:1027:22: warning: dereference of noderef expression drivers/mailbox/arm_mhuv2.c:1048:17: warning: dereference of noderef expression Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-02-14mailbox: qcom: Add support for SDX55 APCS IPCManivannan Sadhasivam1-1/+6
In SDX55, the IPC bits are located in the APCS GCC block. Also, this block can provide clock functionality. Hence, add support for IPC with correct offset and name of the clock provider. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-02-14mailbox: omap: Add support for K3 AM64x SoCsSuman Anna1-1/+5
The AM64x SoC contains a Mailbox IP instance with multiple clusters in the MAIN domain, and is a variant of the IP on current AM65x and J721E SoCs. The AM64x SoC has only 8 clusters with no interrupts routed to the A53 core on the first 2 clusters. The interrupt outputs from the IP do not go through any Interrupt Routers and are hard-wired to each processor, with only couple of interrupts from each cluster reaching the A53 core. The IP is also not built with the K3 safety feature in hardware. Add the support for this IP through a new compatible. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-02-14mailbox: qcom: Add SC8180X apcs compatibleBjorn Andersson1-0/+1
The Qualcomm SC8180X platform has a APSS block exposing the usual IPC bits, add a compatible for this. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-12-09mailbox: arm_mhuv2: Add driverViresh Kumar3-0/+1145
This adds driver for the ARM MHUv2 (Message Handling Unit) mailbox controller. This is based on the accepted DT bindings of the controller and supports combination of both transport protocols, i.e. doorbell and data-transfer. Transmitting and receiving data through the mailbox framework is done through struct arm_mhuv2_mbox_msg. Based on the initial work done by Morten Borup Petersen from ARM. Co-developed-by: Tushar Khandelwal <tushar.khandelwal@arm.com> Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com> Tested-by: Usama Arif <usama.arif@arm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-12-01mailbox: stm32-ipcc: cast void pointers to unsigned longMartin Kaiser1-6/+6
Now that the driver can be enabled by COMPILE_TEST, we see warnings on 64bit platforms when void pointers are cast to unsigned int (and vice versa). warning: cast to smaller integer type 'unsigned int' from 'void *' unsigned int chan = (unsigned int)link->con_priv; ... warning: cast to 'void *' from smaller integer type 'unsigned int' ipcc->controller.chans[i].con_priv = (void *)i; Update these casts to use unsigned long variables, which are the same size as pointers on all platforms. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Martin Kaiser <martin@kaiser.cx> Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-12-01mailbox: stm32-ipcc: remove duplicate error messageMartin Kaiser1-3/+0
platform_get_irq_byname already prints an error message if the requested irq was not found. Don't print another message in the driver. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-12-01mailbox: stm32-ipcc: add COMPILE_TEST dependencyMartin Kaiser1-1/+1
This allows compiling the driver on architectures where the hardware is not available. Most other mailbox drivers support this as well. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-12-01mailbox: arm_mhu_db: Fix mhu_db_shutdown by replacing kfree with devm_kfreeSudeep Holla1-1/+1
The mhu_db_channel info is allocated per channel using devm_kzalloc from mhu_db_mbox_xlate which gets called from mbox_request_channel. However we are releasing the allocated mhu_db_channel info using plain kfree from mhu_db_shutdown which is called from mbox_free_channel. This leads to random crashes when the channel is freed like below one: Unable to handle kernel paging request at virtual address 0080000400000008 [0080000400000008] address between user and kernel address ranges Internal error: Oops: 96000044 [#1] PREEMPT SMP Modules linked in: scmi_module(-) CPU: 1 PID: 2212 Comm: rmmod Not tainted 5.10.0-rc5 #31 Hardware name: ARM LTD ARM Juno Development Platform/ARM Juno Development Platform, BIOS EDK II Nov 19 2020 pstate: 20000085 (nzCv daIf -PAN -UAO -TCO BTYPE=--) pc : release_nodes+0x74/0x230 lr : devres_release_all+0x40/0x68 Call trace: release_nodes+0x74/0x230 devres_release_all+0x40/0x68 device_release_driver_internal+0x12c/0x1f8 driver_detach+0x58/0xe8 bus_remove_driver+0x64/0xe0 driver_unregister+0x38/0x68 platform_driver_unregister+0x1c/0x28 scmi_driver_exit+0x38/0x44 [scmi_module] __arm64_sys_delete_module+0x188/0x260 el0_svc_common.constprop.0+0x80/0x1a8 do_el0_svc+0x2c/0x98 el0_sync_handler+0x160/0x168 el0_sync+0x174/0x180 Code: 1400000d eb07009f 54000460 f9400486 (f90004a6) ---[ end trace c55ffd306c140233 ]--- Fix it by replacing kfree with devm_kfree as required. Fixes: 7002ca237b21 ("mailbox: arm_mhu: Add ARM MHU doorbell driver") Reported-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Tested-by: Cristian Marussi <cristian.marussi@arm.com> Reviewed-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-10-24Merge tag 'armsoc-drivers' of ↵Linus Torvalds1-1/+8
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC-related driver updates from Olof Johansson: "Various driver updates for platforms. A bulk of this is smaller fixes or cleanups, but some of the new material this time around is: - Support for Nvidia Tegra234 SoC - Ring accelerator support for TI AM65x - PRUSS driver for TI platforms - Renesas support for R-Car V3U SoC - Reset support for Cortex-M4 processor on i.MX8MQ There are also new socinfo entries for a handful of different SoCs and platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (131 commits) drm/mediatek: reduce clear event soc: mediatek: cmdq: add clear option in cmdq_pkt_wfe api soc: mediatek: cmdq: add jump function soc: mediatek: cmdq: add write_s_mask value function soc: mediatek: cmdq: add write_s value function soc: mediatek: cmdq: add read_s function soc: mediatek: cmdq: add write_s_mask function soc: mediatek: cmdq: add write_s function soc: mediatek: cmdq: add address shift in jump soc: mediatek: mtk-infracfg: Fix kerneldoc soc: amlogic: pm-domains: use always-on flag reset: sti: reset-syscfg: fix struct description warnings reset: imx7: add the cm4 reset for i.MX8MQ dt-bindings: reset: imx8mq: add m4 reset reset: Fix and extend kerneldoc reset: reset-zynqmp: Added support for Versal platform dt-bindings: reset: Updated binding for Versal reset driver reset: imx7: Support module build soc: fsl: qe: Remove unnessesary check in ucc_set_tdm_rxtx_clk soc: fsl: qman: convert to use be32_add_cpu() ...
2020-10-16mailbox: avoid timer start from callbackJassi Brar1-5/+7
If the txdone is done by polling, it is possible for msg_submit() to start the timer while txdone_hrtimer() callback is running. If the timer needs recheduling, it could already be enqueued by the time hrtimer_forward_now() is called, leading hrtimer to loudly complain. WARNING: CPU: 3 PID: 74 at kernel/time/hrtimer.c:932 hrtimer_forward+0xc4/0x110 CPU: 3 PID: 74 Comm: kworker/u8:1 Not tainted 5.9.0-rc2-00236-gd3520067d01c-dirty #5 Hardware name: Libre Computer AML-S805X-AC (DT) Workqueue: events_freezable_power_ thermal_zone_device_check pstate: 20000085 (nzCv daIf -PAN -UAO BTYPE=--) pc : hrtimer_forward+0xc4/0x110 lr : txdone_hrtimer+0xf8/0x118 [...] This can be fixed by not starting the timer from the callback path. Which requires the timer reloading as long as any message is queued on the channel, and not just when current tx is not done yet. Fixes: 0cc67945ea59 ("mailbox: switch to hrtimer for tx_complete polling") Reported-by: Da Xue <da@libre.computer> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-10-12maiblox: mediatek: Fix handling of platform_get_irq() errorKrzysztof Kozlowski1-5/+3
platform_get_irq() returns -ERRNO on error. In such case casting to u32 and comparing to 0 would pass the check. Fixes: 623a6143a845 ("mailbox: mediatek: Add Mediatek CMDQ driver") Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
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