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2020-06-10mailbox: qcom: Add ipq6018 apcs compatibleSivaprakash Murugesan1-0/+5
The Qualcomm ipq6018 has apcs block, add compatible for the same. Also, the ipq6018 apcs provides a clock functionality similar to msm8916 but the clock driver is different. Create a child device based on the apcs compatible for the clock controller functionality. Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-06-10mailbox: qcom: Add clock driver name in apcs mailbox driver dataSivaprakash Murugesan1-18/+38
Some apcs mailbox devices supports a clock driver, the compatible strings of devices supporting clock driver along with the clock driver name are maintained in a separate structure within the mailbox driver. And the clock driver is added based on device match. With increase in number of devices supporting the clock feature move the clock driver name inside the driver data. so that we can use a single API to get the register offset of mailbox driver and clock driver name together, and the clock driver will be added based on the driver data. Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-06-07mailbox: imx: ONLY IPC MU needs IRQF_NO_SUSPEND flagAnson Huang1-2/+7
IPC MU has no power domain assigned and there could be IPC during noirq suspend phase, so IRQF_NO_SUSPEND flag is needed for IPC MU. However, for other MUs, they have power domain assigned and their power will be turned off during noirq suspend phase, but with IRQF_NO_SUSPEND set, their interrupts are NOT disabled even after their power turned off, it will cause system crash when mailbox driver trys to handle pending interrupts but the MU power is already turned off. So, IRQF_NO_SUSPEND flag should ONLY be added to IPC MU which has power domain managed by SCU, then all other MUs' pending interrupts after noirq suspend phase will be handled after system resume. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-06-07mailbox: imx: Add runtime PM callback to handle MU clocksAnson Huang1-3/+29
Some of i.MX8M SoCs have MU clock, they need to be managed in runtime to make sure the MU clock can be off in runtime, add runtime PM callback to handle MU clock. And on i.MX8MP, the MU clock is combined with power domain and runtime PM is enabled for the clock driver, during noirq suspend/resume phase, runtime PM is disabled by device suspend, but the MU context save/restore needs to enable MU clock for register access, calling clock prepare/enable will trigger runtime resume failure and lead to system suspend failed. Actually, the MU context save/restore is ONLY necessary for SCU IPC MU, other MUs especially on i.MX8MP platforms which have MU clock assigned, they need to runtime request/free mailbox channel in the consumer driver, so no need to save/restore MU context for them, hence it can avoid this issue, so the MU context save/restore is ONLY applied to i.MX platforms MU instance without clock present. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-06-07mailbox: imx: Add context save/restore for suspend/resumeDong Aisheng1-0/+35
For "mem" mode suspend on i.MX8 SoCs, MU settings could be lost because its power is off, so save/restore is needed for MU settings during suspend/resume. However, the restore can ONLY be done when MU settings are actually lost, for the scenario of settings NOT lost in "freeze" mode suspend, since there could be still IPC going on multiple CPUs, restoring the MU settings could overwrite the TIE by mistake and cause system freeze, so need to make sure ONLY restore the MU settings when it is powered off, Anson fixes this by checking whether restore is actually needed when resume. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-05-30mailbox: Add support for Qualcomm IPCCManivannan Sadhasivam3-0/+298
Add support for the Inter-Processor Communication Controller (IPCC) block from Qualcomm that coordinates the interrupts (inbound & outbound) for Multiprocessor (MPROC), COMPUTE-Level0 (COMPUTE-L0) & COMPUTE-Level1 (COMPUTE-L1) protocols for the Application Processor Subsystem (APSS). This driver is modeled as an irqchip+mailbox driver. The irqchip part helps in receiving the interrupts from the IPCC clients such as modems, DSPs, PCI-E etc... and forwards them to respective entities in APSS. On the other hand, the mailbox part is used to send interrupts to the IPCC clients from the entities of APSS. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> [mani: moved to mailbox, added static mbox channels and cleanups] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-05-30mailbox: zynqmp-ipi: Fix NULL vs IS_ERR() check in zynqmp_ipi_mbox_probe()Wei Yongjun1-12/+8
In case of error, the function devm_ioremap() returns NULL pointer not ERR_PTR(). So we should check whether the return value of devm_ioremap() is NULL instead of IS_ERR. Fixes: 4981b82ba2ff ("mailbox: ZynqMP IPI mailbox controller") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-05-30mailbox: imx-mailbox: fix scu msg header size checkPeng Fan1-5/+9
The i.MX8 SCU message header size is the number of "u32" elements, not "u8", so fix the check. Reported-by: coverity-bot <keescook+coverity-bot@chromium.org> Addresses-Coverity-ID: 1461658 ("Memory - corruptions") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Acked-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-05-30mailbox: sprd: Add Spreadtrum mailbox driverBaolin Wang3-0/+371
The Spreadtrum mailbox controller supports 8 channels to communicate with MCUs, and it contains 2 different parts: inbox and outbox, which are used to send and receive messages by IRQ mode. Signed-off-by: Baolin Wang <baolin.wang@unisoc.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-05-30mailbox: ZynqMP IPI: Delete an error message in zynqmp_ipi_probe()Markus Elfring1-3/+2
The function platform_get_irq can log an error already. Thus omit a redundant message for the exception handling in the calling function. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-05-30mailbox: imx: Disable the clock on devm_mbox_controller_register() failureFabio Estevam1-1/+3
devm_mbox_controller_register() may fail, and in the case of failure the priv->clk clock that was previously enabled, should be disabled. Fixes: 2bb7005696e2 ("mailbox: Add support for i.MX messaging unit") Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Acked-by: Oleksij Rempel <o.rempel@pengutronix.de> [Jassi: fixed merge/am conflict] Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-05-30mailbox: imx: Fix return in imx_mu_scu_xlate()Dan Carpenter1-1/+1
This called from mbox_request_channel(). The caller is expecting error pointers and not NULL so this "return NULL;" will lead to an Oops. Fixes: 0a67003b1985 ("mailbox: imx: add SCU MU support") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-05-30mailbox: imx: Support runtime PMAnson Huang1-1/+26
Some power hungry sub-systems like VPU has its own MUs which also use mailbox driver, current mailbox driver uses platform driver model and MU's power will be ON after driver probed and left ON there, it may cause the whole sub-system can NOT enter lower power mode, take VPU driver for example, it has runtime PM support, but due to its MU always ON, the VPU sub-system will be always ON and consume many power during kernel idle. To save power in kernel idle, mailbox driver needs to support runtime PM in order to power off MU when it is unused. However, the runtime suspend/resume can ONLY be implemented in mailbox's .shutdown/.startup callback, so its consumer needs to call mbox_request_channel()/mbox_free_channel() in consumer driver's runtime PM callback, then the MU's power will be ON/OFF along with consumer's runtime PM status. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-05-30mailbox: pcc: make pcc_mbox_driver staticJason Yan1-1/+1
Fix the following sparse warning: drivers/mailbox/pcc.c:571:24: warning: symbol 'pcc_mbox_driver' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Jason Yan <yanaijie@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19mailbox: imx: add SCU MU supportPeng Fan1-0/+155
i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A cores from hardware design, and could not be reused for other purpose. Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples", Passing short messages: Transmit register(s) can be used to pass short messages from one to four words in length. For example, when a four-word message is desired, only one of the registers needs to have its corresponding interrupt enable bit set at the receiver side; the message’s first three words are written to the registers whose interrupt is masked, and the fourth word is written to the other register (which triggers an interrupt at the receiver side). i.MX8/8X SCU firmware IPC is an implementation of passing short messages. But current imx-mailbox driver only support one word message, i.MX8/8X linux side firmware has to request four TX and four RX to support IPC to SCU firmware. This is low efficent and more interrupts triggered compared with one TX and one RX. To make SCU MU work, - parse the size of msg. - Only enable TR0/RR0 interrupt for transmit/receive message. - For TX/RX, only support one TX channel and one RX channel - For RX, support receive msg larger than 4 u32 words. - Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB. Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19mailbox: imx: restructure code to make easy for new MUPeng Fan1-54/+83
Add imx_mu_generic_tx for data send and imx_mu_generic_rx for interrupt data receive. Pack original mu chans related code into imx_mu_init_generic Add tx/rx/init hooks into imx_mu_dcfg With these, it will be a bit easy to introduce i.MX8/8X SCU type MU dedicated to communicate with SCU. Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19mailbox: mediatek: remove implementation related to atomic_execBibby Hsieh1-68/+8
After implement flush, client can flush the executing command buffer or abort the still waiting for event command buffer, so controller do not need to implement atomic_exe feature. remove it. Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19mailbox: mediatek: implement flush functionBibby Hsieh1-0/+52
For client driver which need to reorganize the command buffer, it could use this function to flush the send command buffer. If the channel doesn't be started (usually in waiting for event), this function will abort it directly. Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19maillbox: bcm-flexrm-mailbox: handle cmpl_pool dma allocation failureRayagonda Kokatanur1-0/+2
Handle 'cmpl_pool' dma memory allocation failure. Fixes: a9a9da47f8e6 ("mailbox: no need to check return value of debugfs_create functions") Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Tyler Hicks <tyhicks@linux.microsoft.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19mailbox: sun6i-msgbox: Add a new mailbox driverSamuel Holland3-0/+337
Allwinner sun6i, sun8i, sun9i, and sun50i SoCs contain a hardware message box used for communication between the ARM CPUs and the ARISC management coprocessor. This mailbox contains 8 unidirectional 4-message FIFOs. Add a driver for it, so it can be used with the Linux mailbox framework. Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19mailbox: bcm-pdc: Use scnprintf() for avoiding potential buffer overflowTakashi Iwai1-10/+10
Since snprintf() returns the would-be-output size instead of the actual output size, the succeeding calls may go beyond the given buffer limit. Fix it by replacing with scnprintf(). Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-03-19mailbox:armada-37xx-rwtm:remove duplicate print in armada_37xx_mbox_probe()Tang Bin1-6/+2
In this function,we don't need dev_err() message because when something goes wrong,platform_get_irq() and devm_platform_ioremap_resource() have print an error message itself, so we should remove duplicate dev_err(). Signed-off-by: Tang Bin <tangbin@cmss.chinamobile.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-01-08mailbox: armada-37xx-rwtm: convert to devm_platform_ioremap_resourceYangtao Li1-4/+1
Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-12-01Merge tag 'mailbox-v5.5' of ↵Linus Torvalds4-51/+62
git://git.linaro.org/landing-teams/working/fujitsu/integration Pull mailbox updates from Jassi Brar: - omap : misc - catch error returned from pm_runtime_put_sync - hisi : misc - drop .owner from platform_driver - stm : change how wakeup is handled - imx : fix - bailout on error and nuke correct irq - imx : add support for imx7ulp platform * tag 'mailbox-v5.5' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: imx: add support for imx v1 mu dt-bindings: mailbox: imx-mu: add imx7ulp MU support mailbox: imx: Clear the right interrupts at shutdown mailbox: imx: Fix Tx doorbell shutdown path mailbox: stm32-ipcc: Update wakeup management mailbox: no need to set .owner platform_driver_register mailbox/omap: Handle if CONFIG_PM is disabled
2019-11-30mailbox: imx: add support for imx v1 muRichard Zhu1-17/+38
There is a version 1.0 MU on i.MX7ULP platform. One new version ID register is added, and it's offset is 0. TRn registers are defined at the offset 0x20 ~ 0x2C. RRn registers are defined at the offset 0x40 ~ 0x4C. SR/CR registers are defined at 0x60/0x64. Extend this driver to support it. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Suggested-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-11-30mailbox: imx: Clear the right interrupts at shutdownDaniel Baluta1-2/+13
Make sure to only clear enabled interrupts keeping count of the connection type. Suggested-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-11-30mailbox: imx: Fix Tx doorbell shutdown pathDaniel Baluta1-1/+3
Tx doorbell is handled by txdb_tasklet and doesn't have an associated IRQ. Anyhow, imx_mu_shutdown ignores this and tries to free an IRQ that wasn't requested for Tx DB resulting in the following warning: [ 1.967644] Trying to free already-free IRQ 26 [ 1.972108] WARNING: CPU: 2 PID: 157 at kernel/irq/manage.c:1708 __free_irq+0xc0/0x358 [ 1.980024] Modules linked in: [ 1.983088] CPU: 2 PID: 157 Comm: kworker/2:1 Tainted: G [ 1.993524] Hardware name: Freescale i.MX8QXP MEK (DT) [ 1.998668] Workqueue: events deferred_probe_work_func [ 2.003812] pstate: 60000085 (nZCv daIf -PAN -UAO) [ 2.008607] pc : __free_irq+0xc0/0x358 [ 2.012364] lr : __free_irq+0xc0/0x358 [ 2.016111] sp : ffff00001179b7e0 [ 2.019422] x29: ffff00001179b7e0 x28: 0000000000000018 [ 2.024736] x27: ffff000011233000 x26: 0000000000000004 [ 2.030053] x25: 000000000000001a x24: ffff80083bec74d4 [ 2.035369] x23: 0000000000000000 x22: ffff80083bec7588 [ 2.040686] x21: ffff80083b1fe8d8 x20: ffff80083bec7400 [ 2.046003] x19: 0000000000000000 x18: ffffffffffffffff [ 2.051320] x17: 0000000000000000 x16: 0000000000000000 [ 2.056637] x15: ffff0000111296c8 x14: ffff00009179b517 [ 2.061953] x13: ffff00001179b525 x12: ffff000011142000 [ 2.067270] x11: ffff000011129f20 x10: ffff0000105da970 [ 2.072587] x9 : 00000000ffffffd0 x8 : 0000000000000194 [ 2.077903] x7 : 612065657266206f x6 : ffff0000111e7b09 [ 2.083220] x5 : 0000000000000003 x4 : 0000000000000000 [ 2.088537] x3 : 0000000000000000 x2 : 00000000ffffffff [ 2.093854] x1 : 28b70f0a2b60a500 x0 : 0000000000000000 [ 2.099173] Call trace: [ 2.101618] __free_irq+0xc0/0x358 [ 2.105021] free_irq+0x38/0x98 [ 2.108170] imx_mu_shutdown+0x90/0xb0 [ 2.111921] mbox_free_channel.part.2+0x24/0xb8 [ 2.116453] mbox_free_channel+0x18/0x28 This bug is present from the beginning of times. Cc: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-11-30mailbox: stm32-ipcc: Update wakeup managementFabien Dessenne1-29/+7
The wakeup specific IRQ management is no more needed to wake up the stm32 platform. A relationship has been established between the EXTI and the RX IRQ, just need to declare the EXTI interrupt instead of the IPCC RX IRQ. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-11-26mailbox: no need to set .owner platform_driver_registerTian Tao1-1/+0
the platform_driver_register will set the .owner to THIS_MODULE Signed-off-by: Tian Tao <tiantao6@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-11-26mailbox/omap: Handle if CONFIG_PM is disabledBrandon Maier1-1/+1
If CONFIG_PM is disabled, pm_runtime_put_sync() returns -ENOSYS. Signed-off-by: Brandon Maier <brandon.maier@rockwellcollins.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-11-12mailbox: tegra: Fix superfluous IRQ error messageJon Hunter1-2/+2
Commit 7723f4c5ecdb ("driver core: platform: Add an error message to platform_get_irq*()") added an error message to avoid drivers having to print an error message when IRQ lookup fails. However, there are some cases where IRQs are optional and so new optional versions of the platform_get_irq*() APIs have been added for these cases. The IRQs for Tegra HSP module are optional because not all instances of the module have the doorbell and all of the shared interrupts. Hence, since the above commit was applied the following error messages are now seen on Tegra194 ... ERR KERN tegra-hsp c150000.hsp: IRQ doorbell not found ERR KERN tegra-hsp c150000.hsp: IRQ shared0 not found The Tegra HSP driver deliberately does not fail if these are not found and so fix the above errors by updating the Tegra HSP driver to use the platform_get_irq_byname_optional() API. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20191011083459.11551-1-jonathanh@nvidia.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-09-17mailbox: qcom-apcs: fix max_register valueJorge Ramirez-Ortiz1-1/+1
The mailbox length is 0x1000 hence the max_register value is 0xFFC. Fixes: c6a8b171ca8e ("mailbox: qcom: Convert APCS IPC driver to use regmap") Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-09-17mailbox: qcom: Add support for IPQ8074 APCSGokul Sriram Palanisamy1-0/+1
Add support of IPQ8074 with IPC register offset as 8. Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-09-17mailbox: qcom: Add support for Qualcomm SM8150 and SC7180 SoCsSibi Sankar1-0/+2
Add the corresponding APSS shared offset for SM8150 and SC7180 SoCs. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-09-17mbox: qcom: replace integer with valid macroJorge Ramirez-Ortiz1-1/+2
Use the correct macro when registering the platform device. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-09-17mbox: qcom: add APCS child device for QCS404Jorge Ramirez-Ortiz1-2/+6
There is clock controller functionality in the APCS hardware block of qcs404 devices similar to msm8916. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-09-17mailbox: mediatek: cmdq: clear the event in cmdq initial flowBibby Hsieh1-0/+5
GCE hardware stored event information in own internal sysram, if the initial value in those sysram is not zero value it will cause a situation that gce can wait the event immediately after client ask gce to wait event but not really trigger the corresponding hardware. In order to make sure that the wait event function is exactly correct, we need to clear the sysram value in cmdq initial flow. Fixes: 623a6143a845 ("mailbox: mediatek: Add Mediatek CMDQ driver") Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-09-17mailbox: mediatek: cmdq: support mt8183 gce functionBibby Hsieh1-0/+1
add mt8183 compatible name for supporting gce function Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-09-17mailbox: mediatek: cmdq: move the CMDQ_IRQ_MASK into cmdq driver dataBibby Hsieh1-5/+7
The interrupt mask and thread number has positive correlation, so we move the CMDQ_IRQ_MASK into cmdq driver data and calculate it by thread number. Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-09-17mailbox: armada-37xx-rwtm: Use device-managed registration APIChuhong Yuan1-13/+1
Use devm_mbox_controller_register to get rid of redundant remove function. Signed-off-by: Chuhong Yuan <hslester96@gmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-07-14Merge tag 'mailbox-v5.3' of ↵Linus Torvalds8-48/+81
git://git.linaro.org/landing-teams/working/fujitsu/integration Pull mailbox updates from Jassi Brar: - stm32: race fix by adding a spinlock - mhu: trim included headers - omap: add support for K3 SoCs - imx: Irq disable fix - bcm: tidy up extracting driver data - tegra: make resume 'noirq' - api: fix error handling * tag 'mailbox-v5.3' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: handle failed named mailbox channel request mailbox: tegra: avoid resume NULL mailboxes mailbox: tegra: hsp: add noirq resume mailbox: bcm-flexrm-mailbox: using dev_get_drvdata directly mailbox: imx: Clear GIEn bit at shutdown mailbox: omap: Add support for TI K3 SoCs dt-bindings: mailbox: omap: Update bindings for TI K3 SoCs mailbox: arm_mhu: reorder header inclusion and drop unneeded ones mailbox: stm32_ipcc: add spinlock to fix channels concurrent access
2019-07-12Merge tag 'driver-core-5.3-rc1' of ↵Linus Torvalds2-29/+7
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core and debugfs updates from Greg KH: "Here is the "big" driver core and debugfs changes for 5.3-rc1 It's a lot of different patches, all across the tree due to some api changes and lots of debugfs cleanups. Other than the debugfs cleanups, in this set of changes we have: - bus iteration function cleanups - scripts/get_abi.pl tool to display and parse Documentation/ABI entries in a simple way - cleanups to Documenatation/ABI/ entries to make them parse easier due to typos and other minor things - default_attrs use for some ktype users - driver model documentation file conversions to .rst - compressed firmware file loading - deferred probe fixes All of these have been in linux-next for a while, with a bunch of merge issues that Stephen has been patient with me for" * tag 'driver-core-5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (102 commits) debugfs: make error message a bit more verbose orangefs: fix build warning from debugfs cleanup patch ubifs: fix build warning after debugfs cleanup patch driver: core: Allow subsystems to continue deferring probe drivers: base: cacheinfo: Ensure cpu hotplug work is done before Intel RDT arch_topology: Remove error messages on out-of-memory conditions lib: notifier-error-inject: no need to check return value of debugfs_create functions swiotlb: no need to check return value of debugfs_create functions ceph: no need to check return value of debugfs_create functions sunrpc: no need to check return value of debugfs_create functions ubifs: no need to check return value of debugfs_create functions orangefs: no need to check return value of debugfs_create functions nfsd: no need to check return value of debugfs_create functions lib: 842: no need to check return value of debugfs_create functions debugfs: provide pr_fmt() macro debugfs: log errors when something goes wrong drivers: s390/cio: Fix compilation warning about const qualifiers drivers: Add generic helper to match by of_node driver_find_device: Unify the match function with class_find_device() bus_find_device: Unify the match callback with class_find_device ...
2019-07-11mailbox: handle failed named mailbox channel requestmorten petersen1-2/+4
Previously, if mbox_request_channel_byname was used with a name which did not exist in the "mbox-names" property of a mailbox client, the mailbox corresponding to the last entry in the "mbox-names" list would be incorrectly selected. With this patch, -EINVAL is returned if the named mailbox is not found. Signed-off-by: Morten Borup Petersen <morten_bp@live.dk> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-07-10mailbox: tegra: avoid resume NULL mailboxesBitan Biswas1-4/+6
If Tegra HSP device tree does not have 'shared irqs', mailboxes pointer is NULL. Add non-NULL HSP mailboxes check in resume callback before tegra_hsp_mailbox_startup() call and prevent NULL pointer exception. Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-07-10mailbox: tegra: hsp: add noirq resumeBitan Biswas1-1/+9
Add noirq resume instead of resume callback for Tegra HSP. Tegra HSP resume needs tegra_hsp_doorbell_startup() call to fix timeout error for tegra_bpmp_transfer() during genpd resume noirq on Jetson TX2. Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-07-10mailbox: bcm-flexrm-mailbox: using dev_get_drvdata directlyFuqian Huang1-4/+2
Several drivers cast a struct device pointer to a struct platform_device pointer only to then call platform_get_drvdata(). To improve readability, these constructs can be simplified by using dev_get_drvdata() directly. Signed-off-by: Fuqian Huang <huangfq.daxian@gmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-07-10mailbox: imx: Clear GIEn bit at shutdownDaniel Baluta1-2/+2
GIEn is enabled at startup for RX doorbell mailboxes so we need to clear the bit at shutdown in order to avoid leaving the interrupt line enabled. Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-07-10mailbox: omap: Add support for TI K3 SoCsSuman Anna2-18/+27
The TI K3 AM65x and J721E family of SoCs have a new Mailbox IP that is based on the existing Mailbox IP present in OMAP architecture based SoCs. Each instance of the legacy OMAP Mailbox IP is now a single cluster within the newer Mailbox IP instance on K3 architecture based SoCs. A single K3 Mailbox IP instance has multiple clusters with each cluster providing the same functionality as the existing OMAP Mailbox IP. Reuse the existing OMAP Mailbox driver to extend the support for this newer IP present within the Main NavSS block on K3 SoCs. The K3 family of SoCs use 64-bit ARMv8 processors for running Linux, so the driver is also enhanced to deal with the differences between the 32-bit message payloads and the 64-bit pointers used by the client drivers. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-07-10mailbox: arm_mhu: reorder header inclusion and drop unneeded onesSudeep Holla1-7/+4
This patch just re-orders some of the headers includes and also drop the ones that are unnecessary. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2019-07-10mailbox: stm32_ipcc: add spinlock to fix channels concurrent accessArnaud Pouliquen1-10/+27
Add spinlock protection on IPCC register update to avoid race condition. Without this fix, stm32_ipcc_set_bits and stm32_ipcc_clr_bits can be called in parallel for different channels. This results in register corruptions. Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com> Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
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