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path: root/drivers/irqchip/irq-brcmstb-l2.c
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2014-12-10Merge branch 'irq-core-for-linus' of ↵Linus Torvalds1-15/+26
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq core updates from Thomas Gleixner: "This is the first (boring) part of irq updates: - support for big endian I/O accessors in the generic irq chip - cleanup of brcmstb/bcm7120 drivers so they can be reused for non ARM SoCs - the usual pile of fixes and updates for the various ARM irq chips" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits) irqchip: dw-apb-ictl: Add PM support irqchip: dw-apb-ictl: Enable IRQ_GC_MASK_CACHE_PER_TYPE irqchip: dw-apb-ictl: Always use use {readl|writel}_relaxed ARM: orion: convert the irq_reg_{readl,writel} calls to the new API irqchip: atmel-aic: Add missing entry for rm9200 irq fixups irqchip: atmel-aic: Rename at91sam9_aic_irq_fixup for naming consistency irqchip: atmel-aic: Add specific irq fixup function for sam9g45 and sam9rl irqchip: atmel-aic: Add irq fixups for at91sam926x SoCs irqchip: atmel-aic: Add irq fixup for RTT block irqchip: brcmstb-l2: Convert driver to use irq_reg_{readl,writel} irqchip: bcm7120-l2: Convert driver to use irq_reg_{readl,writel} irqchip: bcm7120-l2: Decouple driver from brcmstb-l2 irqchip: bcm7120-l2: Extend driver to support 64+ bit controllers irqchip: bcm7120-l2: Use gc->mask_cache to simplify suspend/resume functions irqchip: bcm7120-l2: Fix missing nibble in gc->unused mask irqchip: bcm7120-l2: Make sure all register accesses use base+offset irqchip: bcm7120-l2, brcmstb-l2: Remove ARM Kconfig dependency irqchip: bcm7120-l2: Eliminate bad IRQ check irqchip: brcmstb-l2: Eliminate dependency on ARM code genirq: Generic chip: Add big endian I/O accessors ...
2014-11-26irqchip: brcmstb-l2: Fix error handling of irq_of_parse_and_mapDmitry Torokhov1-2/+2
Return value of irq_of_parse_and_map() is unsigned int, with 0 indicating failure, so testing for negative result never works. Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Kevin Cernekee <cernekee@gmail.com> Link: https://lkml.kernel.org/r/20141114221642.GA37468@dtor-ws Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-09irqchip: brcmstb-l2: Convert driver to use irq_reg_{readl,writel}Kevin Cernekee1-12/+22
This effectively converts the __raw_ accessors to the non-__raw_ equivalents. To handle BE, we pass IRQ_GC_BE_IO, similar to what was done in irq-bcm7120-l2.c. Since irq_reg_writel now takes an irq_chip_generic argument, writel must be used for the initial hardware reset in the probe function. But that operation never needs endian swapping, so it's probably not a big deal. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://lkml.kernel.org/r/1415342669-30640-15-git-send-email-cernekee@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-09irqchip: brcmstb-l2: Eliminate dependency on ARM codeKevin Cernekee1-3/+4
The irq-brcmstb-l2 driver has a single dependency on the ARM code, the do_bad_IRQ macro. Expand this macro in-place so that the driver can be built on non-ARM platforms. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lkml.kernel.org/r/1415342669-30640-6-git-send-email-cernekee@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-06-21irqchip: brcmstb-l2: Level-2 interrupts are edge sensitiveFlorian Fainelli1-1/+1
The driver was configuring the interrupt handler for the Level-2 interrupts to be "level" triggered while they are in fact "edge" triggered. Fix this by using the correct handler. Reported-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lkml.kernel.org/r/1402337102-19428-1-git-send-email-f.fainelli@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-05-27irqchip: brcmstb-l2: Add Broadcom Set Top Box Level-2 interrupt controllerFlorian Fainelli1-0/+202
This patch adds support for the Level-2 interrupt controller hardware found in Broadcom Set Top Box System-on-a-Chip devices. This interrupt controller is implemented using the generic IRQ chip driver with separate enable and disable registers. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Link: https://lkml.kernel.org/r/1400892054-24457-2-git-send-email-f.fainelli@gmail.com Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>