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The labels and branching order of the error path of 'aspeed_adc_probe()'
are broken.
Re-order the labels and goto statements.
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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The ASPEED SoC must deassert a reset in order to use the ADC peripheral.
The device tree bindings are updated to document the resets phandle, and
the example is updated to match what is expected for both the reset and
clock phandle. Note that the bindings should have always had the reset
controller, as the hardware is unusable without it.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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The equivalent of both of these are now done via macro magic when
the relevant register calls are made. The actual structure
elements will shortly go away.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Lars-Peter Clausen <lars@metafoo.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into staging-linus
Jonathan writes:
First set of IIO fixes for the 4.13 cycle.
* ad2s1210
- Fix negative angular velocity reads (identified by a gcc 7 warning)
* aspeed-adc
- Wait for initialization sequence to finish before enabling channels.
Without it no channels work.
* axp288
- Revert a patch that dropped some bogus register mods. No one is entirely
sure why but it breaks charging on some devices.
- Fix GPADC pin read returning 0. Turns out a small sleep is needed.
* bmc150
- Make sure device is restored to normal state after suspend / resume
cycle. Otherwise, simple sysfs reads are broken.
* tsl2563
- fix wrong event code.
* st-accel
- add spi 3-wire support. Needed to fix the lsm303agr accelerometer
which only had 3 wires in all cases. Side effect is to enable optional
3-wire support for other devices.
* st-pressure
- disable multiread by default for LPS22HB (only effects SPI)
* sun4i-gpadc-iio
- fix unbalanced irq enable / disable
* vf610
- Fix VALT slection for REFSEL bits - ensures we are using the
right reference pins.
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This patch enables adc engine at initialization time and waits
for the initial sequence completion before enabling adc channels.
Without this code adc channels are not functional and shows
zeros for all connected channels.
Tested on mellanox msn platform.
v1 -> v2:
Pointed by Rick Altherr:
- Wait init sequence code enabled by bool
from OF match table.
Signed-off-by: Mykola Kostenok <c_mykolak@mellanox.com>
Reviewed-by: Rick Altherr <raltherr@google.com>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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clk_prepare_enable() can fail here and we must check its return value.
Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Reviewed-by: Rick Altherr <raltherr@google.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
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Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
interrupts are supported by the hardware but are not currently implemented.
Signed-off-by: Rick Altherr <raltherr@google.com>
Tested-by: Xo Wang <xow@google.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
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