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2022-03-04drm/amdgpu: use job and ib structures directly in CS parsersChristian König9-114/+130
Instead of providing the ib index provide the job and ib pointers directly to the patch and parse functions for UVD and VCE. Also move the set/get functions for IB values to the IB declerations. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-04drm/amdgpu: header cleanupChristian König10-100/+132
No function change, just move a bunch of definitions from amdgpu.h into separate header files. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-04drm/amd/amdgpu: set disabled vcn to no_schdulerJingwen Chen1-0/+2
[Why] after the reset domain introduced, the sched.ready will be init after hw_init, which will overwrite the setup in vcn hw_init, and lead to vcn ib test fail. [How] set disabled vcn to no_scheduler Fixes: 5fd8518d187ed0 ("drm/amdgpu: Move scheduler init to after XGMI is ready") Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com> Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-04drm/amdgpu: install ctx entities with cmpxchgChristian König1-1/+7
Since we removed the context lock we need to make sure that not two threads are trying to install an entity at the same time. Signed-off-by: Christian König <christian.koenig@amd.com> Fixes: 461fa7b0ac565e ("drm/amdgpu: remove ctx->lock") Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-04drm/amdkfd: implement get_atc_vmid_pasid_mapping_info for gfx10.3Yifan Zhang1-1/+15
This patch implements get_atc_vmid_pasid_mapping_info for gfx10.3 Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-04drm/amdkfd: judge get_atc_vmid_pasid_mapping_info before callYifan Zhang1-8/+10
Fix the NULL point issue: [ 3076.255609] BUG: kernel NULL pointer dereference, address: 0000000000000000 [ 3076.255624] #PF: supervisor instruction fetch in kernel mode [ 3076.255637] #PF: error_code(0x0010) - not-present page [ 3076.255649] PGD 0 P4D 0 [ 3076.255660] Oops: 0010 [#1] SMP NOPTI [ 3076.255669] CPU: 20 PID: 2415 Comm: kfdtest Tainted: G W OE 5.11.0-41-generic #45~20.04.1-Ubuntu [ 3076.255691] Hardware name: AMD Splinter/Splinter-RPL, BIOS VS2326337N.FD 02/07/2022 [ 3076.255706] RIP: 0010:0x0 [ 3076.255718] Code: Unable to access opcode bytes at RIP 0xffffffffffffffd6. [ 3076.255732] RSP: 0018:ffffb64283e3fc10 EFLAGS: 00010297 [ 3076.255744] RAX: 0000000000000000 RBX: 0000000000000008 RCX: 0000000000000027 [ 3076.255759] RDX: ffffb64283e3fc1e RSI: 0000000000000008 RDI: ffff8c7a87f60000 [ 3076.255776] RBP: ffffb64283e3fc78 R08: ffff8c7d88518ac0 R09: ffffb64283e3fa60 [ 3076.255791] R10: 0000000000000001 R11: 0000000000000001 R12: 000000000000000f [ 3076.255805] R13: ffff8c7bdcea5800 R14: ffff8c7a9f3f3000 R15: ffff8c7a8696bc00 [ 3076.255820] FS: 0000000000000000(0000) GS:ffff8c7d88500000(0000) knlGS:0000000000000000 [ 3076.255839] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 3076.255851] CR2: ffffffffffffffd6 CR3: 0000000109e3c000 CR4: 0000000000750ee0 [ 3076.255866] PKRU: 55555554 [ 3076.255873] Call Trace: [ 3076.255884] dbgdev_wave_reset_wavefronts+0x72/0x160 [amdgpu] [ 3076.256025] process_termination_cpsch.cold+0x26/0x2f [amdgpu] [ 3076.256182] ? ktime_get_mono_fast_ns+0x4e/0xa0 [ 3076.256196] kfd_process_dequeue_from_all_devices+0x49/0x70 [amdgpu] [ 3076.256328] kfd_process_notifier_release+0x187/0x2b0 [amdgpu] [ 3076.256451] ? mn_itree_inv_end+0xdc/0x110 [ 3076.256463] __mmu_notifier_release+0x74/0x1f0 [ 3076.256474] exit_mmap+0x170/0x200 [ 3076.256484] ? __handle_mm_fault+0x677/0x920 [ 3076.256496] ? _cond_resched+0x19/0x30 [ 3076.256507] mmput+0x5d/0x130 [ 3076.256518] do_exit+0x332/0xaf0 [ 3076.256526] ? handle_mm_fault+0xd7/0x2b0 [ 3076.256537] do_group_exit+0x43/0xa0 [ 3076.256548] __x64_sys_exit_group+0x18/0x20 [ 3076.256559] do_syscall_64+0x38/0x90 [ 3076.256569] entry_SYSCALL_64_after_hwframe+0x44/0xa9 Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-04drm/amdgpu/vcn: Add vcn firmware logRuijing Dong9-1/+163
vcn fwlog is for debugging purpose only, by default, it is disabled. Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-04drm/amdgpu/vcn: Update fw shared data structureRuijing Dong5-35/+61
Add fw log in fw shared data structure. Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-04drm/amdgpu: Add DFC CAP support for aldebaranDavid Yu2-1/+2
Add DFC CAP support for aldebaran Initialize cap microcode in psp_init_sriov_microcode, the ta microcode will be initialized in psp_vxx_init_microcode Signed-off-by: David Yu <David.Yu@amd.com> Reviewed-by: Shaoyun.liu <Shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-04drm/amdgpu: Set correct DMA mask for aldebaranHarish Kasiviswanathan1-3/+4
Aldebaran has 48-bit physical address support Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-04drm/amdgpu: Refactor mode2 reset logic for v13.0.2Lijo Lazar2-20/+54
Use IP version and refactor reset logic to apply to a list of devices. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-04drm/amd/display: 3.2.175Aric Cyr1-1/+1
drm/amd/display: 3.2.175 This version brings along following fixes: - Remove invalid RDPCS Programming in DAL - Make functional resource functions non-static - Reset VIC if HDMI_VIC is present - Add frame alternate 3D & restrict HW packed on dongles - Reg to turn on/off PSR Power seq in FSM - Modify plane removal sequence to avoid hangs - Pass HostVM enable flag into DCN3.1 DML - DC Validation failures - Program OPP before ODM - Refactor fixed VS w/a for PHY tests - Pass deep sleep disabled allow info to dmub fw - Refine the EDID override - [FW Promotion] Release 0.0.106.0 - Add verify_link_cap back for hdmi Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-04drm/amd/display: add verify_link_cap back for hdmiCharlene Liu1-1/+2
[why] hdmi specific: add verify link cap after retrive link cap. Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-04drm/amd/display: [FW Promotion] Release 0.0.106.0Anthony Koo1-2/+2
Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-04drm/amd/display: refine the EDID overridejinzh1-0/+3
[Why] We already get the SBIOS EDID via ACPI on KMD, but after that, we just use the monitor EDID to set it HDR caps [How] Make the SBIOS EDID override to read_edid() That can change the read EDID caps from the right EDID Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: jinzh <jinzh@github.amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-04drm/amd/display: Pass deep sleep disabled allow info to dmub fwRobin Chen1-0/+1
[Why] The deep sleep mode need to be disabled in some PSR scenario. Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Robin Chen <robin.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-04drm/amd/display: Refactor fixed VS w/a for PHY testsGeorge Shen1-5/+11
[Why/How] Refactor original w/a to unify naming and simplify logic. This also re-enables the code that was previously skipped due to the disabling of the previous workaround logic. Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: George Shen <George.Shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-04drm/amd/display: Program OPP before ODMWesley Chalmers1-24/+25
[WHY] HW expects OPP to be configured before ODM is enabled. Failure to do so can cause errors. Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-04drm/amd/display: Pass HostVM enable flag into DCN3.1 DMLMichael Strauss1-0/+1
[WHY] Calculations differ with HostVM enabled/disabled, causing underflow in configs with high refresh displays + scaling due to lower available BW [HOW] Check riommu_active in order to pass correct HostVM enablement to DML Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Michael Strauss <michael.strauss@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: remove redundant null checkWeiguo Li1-6/+0
Remove the redundant null check since the caller ensures that 'ctx' is never NULL. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Weiguo Li <liwg06@foxmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu/sdma5: drop unused cyan skillfish firmwareAlex Deucher1-7/+1
Leftover from bring up. Not used anymore. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu/gfx10: drop unused cyan skillfish firmwareAlex Deucher1-11/+1
Leftover from bring up. Not used anymore. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: remove unused gpu_info firmwaresAlex Deucher1-23/+0
These were leftover from bring up and are no longer necessary. The information is available via the IP discovery table. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: Use IP versions in convert_tiling_flags_to_modifier()Alex Deucher1-3/+3
Rather than checking the asic_type. Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amd/display: Modify plane removal sequence to avoid hangs.Dillon Varone2-6/+6
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amd/pm: new v3 SmuMetrics data structure for Sienna CichlidDanijel Slivka2-61/+178
structure changed in smc_fw_version >= 0x3A4900, "uint16_t VcnActivityPercentage" replaced with "uint16_t VcnUsagePercentage0" and "uint16_t VcnUsagePercentage1" Signed-off-by: Danijel Slivka <danijel.slivka@amd.com> Acked-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: enable gfxoff routine for GC 10.3.7Prike Liang2-0/+4
Enable gfxoff routine for GC 10.3.7. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: enable gfx power gating for GC 10.3.7Prike Liang2-1/+4
Enable gfx power gating for GC 10.3.7. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu/nv: enable clock gating for GC 10.3.7 subblockPrike Liang1-1/+11
This will enable the following block clock gating. - MC - SDMA - HDP - ATHUB - IH - VCN/JPEG Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: enable gfx clock gating control for GC 10.3.7Prike Liang1-0/+1
Enable gfx cg gate/ungate control for GC 10.3.7. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: fix suspend/resume hang regressionQiang Yu1-1/+2
Regression has been reported that suspend/resume may hang with the previous vm ready check commit. So bring back the evicted list check as a temp fix. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1922 Fixes: c1a66c3bc425 ("drm/amdgpu: check vm ready by amdgpu_vm->evicting flag") Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Qiang Yu <qiang.yu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: Move CAP firmware loading to the beginning of PSP firmware listYifan Zha1-2/+2
[Why] As PSP needs to verify the signature, CAP firmware must be loaded first when PSP loads firmwares. Otherwise, when DFC feature is enabled, CP firmwares would be loaded failed. [ 1149.160480] [drm] MM table gpu addr = 0x800022f000, cpu addr = 00000000a62afcea. [ 1149.209874] [drm] failed to load ucode CP_CE(0x8) [ 1149.209878] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007) [ 1149.215914] [drm] failed to load ucode CP_PFP(0x9) [ 1149.215917] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007) [ 1149.221941] [drm] failed to load ucode CP_ME(0xA) [ 1149.221944] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007) [ 1149.228082] [drm] failed to load ucode CP_MEC1(0xB) [ 1149.228085] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007) [ 1149.234209] [drm] failed to load ucode CP_MEC2(0xD) [ 1149.234212] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007) [ 1149.242379] [drm] failed to load ucode VCN(0x1C) [ 1149.242382] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0xFFFF0007) [How] Move CAP UCODE ID to the beginning of AMDGPU_UCODE_ID enum list. Signed-off-by: Yifan Zha <Yifan.Zha@amd.com> Reviewed-by: Bokun Zhang <Bokun.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: Bump minor version for hot plug tests enabling.Andrey Grodzovsky1-1/+2
This will allow to enable the tests only after latest fix after which the tests passed on my system. I tested on NV21 standalone and Vega 10 and Polaris as pair with DRI_PRIME. It's possible there might be still issues on ASICs i don't have at my posession but that that the point of enbling the tests finally - if other people during testing will encounter errors they will report and I will be able to fix. The releated merge request for enabling libdrm tests suite is in https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/227 Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: Fix sigsev when accessing MMIO on hot unplug.Andrey Grodzovsky1-2/+8
Protect with drm_dev_enter/exit Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: convert code name to ip version for noretry setYifan Zhang1-6/+5
Use IP version rather than codename for noretry set. Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: move amdgpu_gmc_noretry_set after ip_versions populatedYifan Zhang1-1/+1
otherwise adev->ip_versions is still empty when amdgpu_gmc_noretry_set is called. Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: Remove redundant .ras_fini initialization in some ras blocksyipechai9-26/+8
1. Define amdgpu_ras_block_late_fini_default in amdgpu_ras.c as .ras_fini common function, which is called when .ras_fini of ras block isn't initialized. 2. Remove the code of using amdgpu_ras_block_late_fini to initialize .ras_fini in ras blocks. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: Remove redundant calls of amdgpu_ras_block_late_fini in mca ras ↵yipechai3-27/+3
block Remove redundant calls of amdgpu_ras_block_late_fini in mca ras block. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: Remove redundant calls of amdgpu_ras_block_late_fini in sdma ras ↵yipechai3-9/+1
block Remove redundant calls of amdgpu_ras_block_late_fini in sdma ras block. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: Remove redundant calls of amdgpu_ras_block_late_fini in hdp ras ↵yipechai3-5/+2
block Remove redundant calls of amdgpu_ras_block_late_fini in hdp ras block. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: Remove redundant calls of amdgpu_ras_block_late_fini in xgmi ras ↵yipechai1-8/+1
block Remove redundant calls of amdgpu_ras_block_late_fini in xgmi ras block. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: Remove redundant calls of amdgpu_ras_block_late_fini in umc ras ↵yipechai4-10/+2
block Remove redundant calls of amdgpu_ras_block_late_fini in umc ras block. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: Remove redundant calls of amdgpu_ras_block_late_fini in nbio ras ↵yipechai3-9/+1
block Remove redundant calls of amdgpu_ras_block_late_fini in nbio ras block. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: Remove redundant calls of amdgpu_ras_block_late_fini in mmhub ↵yipechai3-5/+2
ras block Remove redundant calls of amdgpu_ras_block_late_fini in mmhub ras block. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: Remove redundant calls of amdgpu_ras_block_late_fini in gfx ras ↵yipechai3-9/+1
block Remove redundant calls of amdgpu_ras_block_late_fini in gfx ras block. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: centrally calls the .ras_fini function of all ras blocksyipechai5-26/+14
centrally calls the .ras_fini function of all ras blocks. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: Optimize xxx_ras_fini function of each ras blockyipechai11-21/+21
1. Move the variables of ras block instance members from specific xxx_ras_fini to general ras_fini call. 2. Function calls inside the modules only use parameters passed from xxx_ras_fini instead of ras block instance members. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amdgpu: Modify .ras_fini function pointer parameteryipechai19-24/+24
Modify .ras_fini function pointer parameter so that we can remove redundant intermediate calls in some ras blocks. Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amd/display: Adding a dc_debug option and dmub setting to use PHY FSM ↵Shah Dharati4-2/+9
for PSR [Why] PSR Power on/off is done in PSR. Add a dc_debug option and dmub setting to use PHY implementation of this instead. [How] Add a dc_debug option and dmub setting to use PHY FSM Power up/down for PSR. Co-authored-by: Shah Dharati <dharati.shah@amd.com> Reviewed-by: Hansen Dsouza <hansen.dsouza@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Shah Dharati <dharati.shah@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-02drm/amd/display: Add frame alternate 3D & restrict HW packed on donglesDillon Varone3-12/+13
[WHY?] Some projectors support frame alternate 3D modes at 120Hz, but DAL3 does not create timings. Most active DP to HDMI dongles do not translate infoframes properly to use HW packing stereo mode. [HOW?] Create frame alternate 3D timings for displays that support it. Disable HW packing 3D mode on DP active dongles. Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-03 21:01:51 +0000