summaryrefslogtreecommitdiffstats
path: root/drivers/gpu
AgeCommit message (Collapse)AuthorFilesLines
2015-12-21drm/amd/powerplay: add Tonga dpm support (v3)yanyang120-12/+9284
This implements DPM for tonga. DPM handles dynamic clock and voltage scaling. v2: merge all the patches related with tonga dpm v3: merge dpm force level fix, cgs display fix, spelling fix Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: yanyang1 <young.yang@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
2015-12-21drm/amd/powerplay: Add Tonga SMU supportJammy Zhou5-2/+921
The SMU manager handles firmware loading for other IP blocks (GFX, SDMA, etc.). This implements it for Tonga. v3: delete peci sub-module v2: use cgs interface directly Signed-off-by: Young Yang <Young.Yang@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amd/powerplay: add header file for tonga smu and dpmyanyang14-198/+1844
These headers provide the SMU interface used by the driver. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: yanyang1 <young.yang@amd.com>
2015-12-21drm/amd/powerplay: Move smu7*.h from amdgpu to powerplay.yanyang13-0/+0
Move smu7.h, smu7_discrete.h and smu7_fusion.h from amdgpu to powerplay. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: yanyang1 <young.yang@amd.com>
2015-12-21drm/amd/powerplay: Add ixSWRST_COMMAND_1 in bif_5_0_d.hyanyang11-0/+1
Add ixSWRST_COMMAND_1 in bif_5_0_d.h. Required by new powerplay code for tonga and fiji. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: yanyang1 <young.yang@amd.com>
2015-12-21drm/amd/powerplay: implement functions of amd_powerplay_funcRex Zhu1-8/+183
This is the common interface for interacting with the powerplay module. v2: squash in fixes Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amd/powerplay: add event manager sub-componentRex Zhu20-1/+2423
The event manager handles power related driver events. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amd/powerplay: add CG and PG support for carrizoRex Zhu10-12/+1058
This adds clock and powergating support for CZ. v2: squash in fixes Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amd/powerplay: add Carrizo dpm supportJammy Zhou4-3/+1212
This patch enables basic DPM support for Carrizo. DPM handles dynamic clock and voltage scaling. v3: delete peci sub-module v2: use cgs interface directly correct define SMU_EnabledFeatureScoreboard_SclkDpmOn Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amd/powerplay: add Carrizo smu supportJammy Zhou8-2/+963
This implements the SMU firmware manager interface for CZ. Some header files are moved from amdgpu folder to powerplay as well. v3: delete peci sub-module. v2: use cgs interface directly add load_mec_firmware function Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amd/powerplay: add hardware manager sub-componentJammy Zhou16-6/+3439
The hwmgr handles all hardware related calls, including clock/power gating control, DPM, read and parse PPTable, etc. v5: squash in fixes v4: implement acpi's atcs function use cgs interface v3: fix code style error and add big-endian mode support. v2: use cgs interface directly in hwmgr sub-module Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amd/powerplay: add SMU manager sub-componentJammy Zhou6-0/+560
The SMUMGR is one sub-component of powerplay for SMU firmware support. The SMU handles firmware loading for other IP blocks (GFX, SDMA, etc.) on VI parts. The adds the core powerplay infrastructure to handle that. v3: direct use printk in powerplay module. v2: direct use cgs_read/write_register functions in smu-modules Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amdgpu: export amd_powerplay_func to amdgpu and other ip blockRex Zhu2-81/+180
Update amdgpu to deal with the new powerplay module properly. v2: squash in fixes v3: squash in Rex's power state reporting fix Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amdgpu: disable legacy path of firmware check if powerplay is enabledRex Zhu2-49/+55
Powerplay will use a different interface once it's integrated. These legacy pathes will be removed once powerplay is enabled by default. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amd/powerplay: add basic powerplay frameworkAlex Deucher12-9/+718
amdgpu_pp_ip_funcs is introduced to handle the two code paths, the legacy one and the new powerplay implementation. CONFIG_DRM_AMD_POWERPLAY kernel configuration option is introduced for the powerplay component. v4: squash in fixes v3: register debugfs file when powerplay module enable v2: add amdgpu_ucode_init_bo in hw init when amdgpu_powerplay enable. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amdgpu: add new cgs interface to get display info (v2)Rex Zhu2-0/+60
Add new CGS interfaces to query display info across modules. This is nedded by the powerplay module for synchronizing with the display module. v2: (agd): fold in refresh rate fix, rebase Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amdgpu: implement cgs interface to query system infoRex Zhu2-0/+46
Add a query to get the bus number and function of the device. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
2015-12-21drm/amdgpu: implement new cgs interface for acpi functionRex Zhu2-3/+262
Add a new driver internal interface for accessing ACPI methods. These will be used by various new components including powerplay. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amdgpu: mv amdgpu_acpi.h to amd/include/amd_acpi.hRex Zhu3-4/+4
This will be shared with the new powerplay module. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amdgpu: mv some definition from amdgpu_acpi.c to amdgpu_acpi.hRex Zhu2-60/+53
These will be shared with the new powerplay module. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amdgpu: share struct amdgpu_pm_state_type with powerplay moduleRex Zhu3-30/+27
rename amdgpu_pm_state_type to amd_pm_state_type Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/radeon: clean up fujitsu quirksAlex Deucher1-9/+3
Combine the two quirks. bug: https://bugzilla.kernel.org/show_bug.cgi?id=109481 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2015-12-21drm/amdgpu: Fix off-by-one errors in amdgpu_vm_bo_mapFelix Kuehling1-5/+5
eaddr is sometimes treated as the last address inside the address range, and sometimes as the first address outside the range. This was resulting in errors when a test filled up the entire address space. Make it consistent to always be the last address within the range. Signed-off-by: Felix.Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org
2015-12-21drm/radeon: Fix off-by-one errors in radeon_vm_bo_set_addrFelix Kuehling1-6/+6
eoffset is sometimes treated as the last address inside the address range, and sometimes as the first address outside the range. This was resulting in errors when a test filled up the entire address space. Make it consistent to always be the last address within the range. Also fixed related errors when checking the VA limit and in radeon_vm_fence_pts. Signed-off-by: Felix.Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org
2015-12-21drm/radeon: fix dp link rate selection (v2)Alex Deucher3-77/+49
Need to properly handle the max link rate in the dpcd. This prevents some cases where 5.4 Ghz is selected when it shouldn't be. v2: simplify logic, add array bounds check Reviewed-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-21drm/amdgpu: fix dp link rate selection (v2)Alex Deucher1-60/+36
Need to properly handle the max link rate in the dpcd. This prevents some cases where 5.4 Ghz is selected when it shouldn't be. v2: simplify logic, add array bounds check Reviewed-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-18drm/radeon: only increment sync_seq when a fence is really emittedNicolai Hähnle1-2/+2
In the rare situation where the kmalloc fails we're probably screwed anyway, but let's try to be more robust about it. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Nicolai Hähnle <Nicolai.Haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-18drm/radeon: fix typo in cik_ring_ib_execute documentation (v2)Nicolai Hähnle1-2/+2
v2: agd: clarify commit message, fix "an" as spotted by Michel. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-18drm/radeon: Update radeon_get_vblank_counter_kms()Thierry Reding1-12/+12
Commit 88e72717c2de ("drm/irq: Use unsigned int pipe in public API") updated the prototype of this function but not the implementation. This wasn't noticed even through compile tests because the prototype is part of the source file that uses it and hence the compiler won't know the prototype when it compiles the implementation. The right thing would've been to move the prototype to a header that's included in radeon_kms.c so that the implementation signature could be checked against it, but the closest thing would've been radeon_drv.h and including that results in a lot of build errors, so we'll leave it as is for now. Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-18drm/radeon: Fixup hw vblank counter/ts for new drm_update_vblank_count() (v2)Mario Kleiner9-29/+164
commit 4dfd6486 "drm: Use vblank timestamps to guesstimate how many vblanks were missed" introduced in Linux 4.4-rc1 makes the drm core more fragile to drivers which don't update hw vblank counters and vblank timestamps in sync with firing of the vblank irq and essentially at leading edge of vblank. This exposed a problem with radeon-kms/amdgpu-kms which do not satisfy above requirements: The vblank irq fires a few scanlines before start of vblank, but programmed pageflips complete at start of vblank and vblank timestamps update at start of vblank, whereas the hw vblank counter increments only later, at start of vsync. This leads to problems like off by one errors for vblank counter updates, vblank counters apparently going backwards or vblank timestamps apparently having time going backwards. The net result is stuttering of graphics in games, or little hangs, as well as total failure of timing sensitive applications. See bug #93147 for an example of the regression on Linux 4.4-rc: https://bugs.freedesktop.org/show_bug.cgi?id=93147 This patch tries to align all above events better from the viewpoint of the drm core / of external callers to fix the problem: 1. The apparent start of vblank is shifted a few scanlines earlier, so the vblank irq now always happens after start of this extended vblank interval and thereby drm_update_vblank_count() always samples the updated vblank count and timestamp of the new vblank interval. To achieve this, the reporting of scanout positions by radeon_get_crtc_scanoutpos() now operates as if the vblank starts radeon_crtc->lb_vblank_lead_lines before the real start of the hw vblank interval. This means that the vblank timestamps which are based on these scanout positions will now update at this earlier start of vblank. 2. The driver->get_vblank_counter() function will bump the returned vblank count as read from the hw by +1 if the query happens after the shifted earlier start of the vblank, but before the real hw increment at start of vsync, so the counter appears to increment at start of vblank in sync with the timestamp update. 3. Calls from vblank irq-context and regular non-irq calls are now treated identical, always simulating the shifted vblank start, to avoid inconsistent results for queries happening from vblank irq vs. happening from drm_vblank_enable() or vblank_disable_fn(). 4. The radeon_flip_work_func will delay mmio programming a pageflip until the start of the real vblank iff it happens to execute inside the shifted earlier start of the vblank, so pageflips now also appear to execute at start of the shifted vblank, in sync with vblank counter and timestamp updates. This to avoid some races between updates of vblank count and timestamps that are used for swap scheduling and pageflip execution which could cause pageflips to execute before the scheduled target vblank. The lb_vblank_lead_lines "fudge" value is calculated as the size of the display controllers line buffer in scanlines for the given video mode: Vblank irq's are triggered by the line buffer logic when the line buffer refill for a video frame ends, ie. when the line buffer source read position enters the hw vblank. This means that a vblank irq could fire at most as many scanlines before the current reported scanout position of the crtc timing generator as the number of scanlines the line buffer can maximally hold for a given video mode. This patch has been successfully tested on a RV730 card with DCE-3 display engine and on a evergreen card with DCE-4 display engine, in single-display and dual-display configuration, with different video modes. A similar patch is needed for amdgpu-kms to fix the same problem. Limitations: - Line buffer sizes in pixels are hard-coded on < DCE-4 to a value i just guessed to be high enough to work ok, lacking info on the true sizes atm. Fixes: fdo#93147 Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Michel Dänzer <michel.daenzer@amd.com> Cc: Harry Wentland <Harry.Wentland@amd.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1) Tested-by: Dave Witbrodt <dawitbro@sbcglobal.net> (v2) Refine radeon_flip_work_func() for better efficiency: In radeon_flip_work_func, replace the busy waiting udelay(5) with event lock held by a more performance and energy efficient usleep_range() until at least predicted true start of hw vblank, with some slack for scheduler happiness. Release the event lock during waits to not delay other outputs in doing their stuff, as the waiting can last up to 200 usecs in some cases. Retested on DCE-3 and DCE-4 to verify it still works nicely. (v2) Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-18drm/radeon: Fix "slow" audio over DP on DCE8+Slava Grigorev4-0/+29
DP audio is derived from the dfs clock. Signed-off-by: Slava Grigorev <slava.grigorev@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2015-12-18drm/amdgpu: keep the PTs validation list in the VM v2Christian König4-47/+27
This avoids allocating it on the fly. v2: fix grammar in comment Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
2015-12-18drm/amdgpu: split VM PD and PT handling during CSChristian König4-29/+51
This way we avoid the extra allocation for the page directory entry. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
2015-12-18drm/amdgpu: put VM page tables directly into duplicates listChristian König4-9/+12
They share the reservation object with the page directory anyway. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
2015-12-18drm/amdgpu: restrict the sched jobs number to power of twoChunming Zhou2-2/+11
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> CC: stable@vger.kernel.org
2015-12-17drm/amdgpu: limit visible vram if it's smaller than the BARAlex Deucher2-0/+8
In some cases the amount of vram may be less than the BAR size, if so, limit visible vram to the amount of actual vram, not the BAR size. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-14drm/amdgpu: change default sched jobs to 32Chunming Zhou1-2/+2
Change the default scheduler queue size from 16 to 32. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-14drm/amdgpu: unify AMDGPU_CTX_MAX_CS_PENDING and amdgpu_sched_jobsChunming Zhou2-10/+20
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-14drm/amdgpu: handle error case for ctxChunming Zhou1-2/+5
Properly handle ctx init failure. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-14drm/amdgpu: add entity only when first job comeChunming Zhou1-5/+8
umd somtimes will create a context for every ring, that means some entities wouldn't be used at all. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-11drm/amdgpu: add more debugging output for driver failuresAlex Deucher1-16/+57
Add more fine grained debugging output for init/fini/suspend/ resume failures. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-11drm/amdgpu: update rev id register for VIFlora Cui1-6/+3
Change-Id: I2ae9bb4a929f7c0c8783e0be563ae04be77596e2 Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-11drm/amdgpu/gfx8: update PA_SC_RASTER_CONFIG:PKR_MAP onlyFlora Cui1-1/+1
Use default value as a base. Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
2015-12-11drm/amdgpu/gfx8: Enable interrupt on ME1_PIPE3Flora Cui1-0/+5
Otherwise FW cannot see the RLC ACK for the memory clean request It's for Stoney. Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
2015-12-04drm/amdgpu: add spin lock to protect freed list in vm (v2)jimqu2-3/+15
there is a protection fault about freed list when OCL test. add a spin lock to protect it. v2: drop changes in vm_fini Signed-off-by: JimQu <jim.qu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2015-12-04amdgpu/gfxv8: Remove magic numbers from function ↵Tom St Denis1-2/+2
gfx_v8_0_tiling_mode_table_init() Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-04drm/amdgpu: fix race condition in amd_sched_entity_push_jobNicolai Hähnle1-2/+3
As soon as we leave the spinlock after the job has been added to the job queue, we can no longer rely on the job's data to be available. I have seen a null-pointer dereference due to sched == NULL in amd_sched_wakeup via amd_sched_entity_push_job and amd_sched_ib_submit_kernel_helper. Since the latter initializes sched_job->sched with the address of the ring scheduler, which is guaranteed to be non-NULL, this race appears to be a likely culprit. Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Bugzilla: https://bugs.freedesktop.org/attachment.cgi?bugid=93079 Reviewed-by: Christian König <christian.koenig@amd.com>
2015-12-04drm/amdgpu: add err check for pin userptrChunming Zhou1-3/+7
Missing error check if the operation failed. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2015-12-04amdgpu/gfxv8: Simplification in gfx_v8_0_enable_gui_idle_interrupt()Tom St Denis1-11/+5
Simplified the function by folding the two paths into one. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-04amdgpu/gfxv8: Simplification of gfx_v8_0_create_bitmask()Tom St Denis1-7/+1
Simplification of the function gfx_v8_0_create_bitmask(). Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-10-03 10:06:44 +0000