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path: root/drivers/gpu
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2016-04-15drm/i915: Compute DSI PLL parameters during .compute_config()Ville Syrjälä5-81/+112
2016-04-15drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHVVille Syrjälä2-68/+80
2016-04-15drm/i915/bxt: PORT_PLL_REF_SEL bit should be set for all BXT variationsDongwon Kim1-10/+2
2016-04-15drm/i915/bxt: Enable runtime PMImre Deak1-1/+1
2016-04-15Revert "drm/i915/bxt: Disable power well support"Imre Deak1-5/+0
2016-04-15drm/i915/bxt: Add HW state verification for DDI PHY and CDCLKImre Deak5-2/+138
2016-04-15drm/i915/bxt: Don't reprogram an already enabled DDI PHYImre Deak1-0/+40
2016-04-15drm/i915/bxt: Sanitize the DBUF HW state together with CDCLKImre Deak1-2/+26
2016-04-15drm/i915/bxt: Don't toggle power well 1 on-demandImre Deak5-48/+66
2016-04-15drm/i915/bxt: Power down DDI PHYs separately during the per PHY uninitImre Deak1-3/+4
2016-04-15drm/i915/bxt: Pass drm_i915_private to DDI PHY, CDCLK helpersImre Deak5-31/+21
2016-04-15drm/i915/skl: Unexport skl_pw1_misc_io_initImre Deak2-33/+18
2016-04-15drm/i915/bxt: Suspend power domains during suspend-to-idleImre Deak1-2/+4
2016-04-15drm/i915/gen9: Fix DMC/DC state assertsImre Deak1-21/+11
2016-04-15drm/i915/gen9: Make power well disabling synchronousImre Deak1-4/+5
2016-04-15drm/i915/gen9: Reset secondary power well requests left on by DMC/KVMRImre Deak1-0/+41
2016-04-15drm/i915/bxt: Add a note about BXT_PORT_CL1CM_DW30 being read-onlyImre Deak1-0/+3
2016-04-15drm/i915/bxt: Fix GRC code register field definitionsImre Deak1-7/+3
2016-04-15drm/i915/bxt: Reject DMC firmware versions with known bugsImre Deak1-5/+15
2016-04-15drm/i915: use drm_crtc_send_vblank_event()Gustavo Padovan1-4/+2
2016-04-14drm/i915: Use fw_domains_put_with_fifo() on HSWVille Syrjälä1-1/+5
2016-04-14drm/i915: Split gen8_gt_irq_handler into ack+handleVille Syrjälä1-32/+47
2016-04-14drm/i915: Eliminate passing dev+dev_priv to {snb,ilk}_gt_irq_handler()Ville Syrjälä1-15/+12
2016-04-14drm/i915: Move gt/pm irq handling out from irq disabled section on VLVVille Syrjälä1-5/+5
2016-04-14drm/i915: Split VLV/CVH PIPESTAT handling into ack+handlerVille Syrjälä1-4/+17
2016-04-14drm/i915: Split PORT_HOTPLUG_STAT ack out from i9xx_hpd_irq_handler()Ville Syrjälä1-17/+30
2016-04-14drm/i915: Move variables to narrower scope in VLV/CHV irq handlersVille Syrjälä1-2/+2
2016-04-14drm/i915: Eliminate loop from VLV irq handlerVille Syrjälä1-4/+3
2016-04-14drm/i915: Clear VLV_IER around irq processingVille Syrjälä1-1/+35
2016-04-14drm/i915: Clear VLV_MASTER_IER around irq processingVille Syrjälä1-6/+10
2016-04-14drm/i915: Clear VLV_IIR after PIPESTATVille Syrjälä1-15/+21
2016-04-14drm/i915: Set up VLV_MASTER_IER consistentlyVille Syrjälä1-0/+5
2016-04-14drm/i915: Use GEN8_MASTER_IRQ_CONTROL consistentlyVille Syrjälä1-3/+3
2016-04-14drm/i915: Ignore GTFIFODBG FIFO free entry fields on CHVVille Syrjälä2-3/+8
2016-04-14drm/i915/mocs: Program MOCS for all engines on initPeter Antoine4-40/+122
2016-04-14drm/i915: Late request cancellations are harmfulChris Wilson6-51/+30
2016-04-14drm/i915: Reorganise legacy context switch to cope with late failureChris Wilson1-74/+67
2016-04-14drm/i915: Split out !RCS legacy context switchingChris Wilson1-36/+38
2016-04-14drm/i915: Move the mb() following release-mmap into release-mmapChris Wilson1-3/+16
2016-04-14drm/i915: Force ringbuffers to not be at offset 0Chris Wilson1-2/+5
2016-04-14drm/i915: Prevent machine death on Ivybridge context switchingChris Wilson1-3/+12
2016-04-14drm/i915: Suppress error message when GPU resets are disabledChris Wilson1-1/+4
2016-04-14drm/i915: Prevent leaking of -EIO from i915_wait_request()Chris Wilson6-38/+32
2016-04-14drm/i915: Simplify reset_counter handling during atomic modesettingChris Wilson1-11/+7
2016-04-14drm/i915: Store the reset counter when constructing a requestChris Wilson6-51/+16
2016-04-14drm/i915: Tighten reset_counter for reset statusChris Wilson5-58/+36
2016-04-14drm/i915: Simplify checking of GPU reset_counter in display pageflipsChris Wilson1-7/+9
2016-04-14drm/i915: Hide the atomic_read(reset_counter) behind a helperChris Wilson7-26/+55
2016-04-14drm/i915: Add GEM debugging Kconfig optionChris Wilson4-7/+52
2016-04-14drm/i915: Disentangle i915_drv.h includesChris Wilson3-12/+21
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