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path: root/drivers/gpu/drm/tegra/sor.c
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2016-11-07drm/tegra: sor: No need to free devm_ allocated memoryChristophe Jaillet1-2/+0
Memory for the brick clock is allocated by devm_kzalloc(), so there is no need here to free it explicitly. The only function that calls tegra_clk_sor_brick_register() is the probe function and it correctly checks and handles the return value, which, on failure, will cause devm_ allocated memory to be freed automatically. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-16Merge tag 'drm/tegra/for-4.8-rc1' of ↵Dave Airlie1-231/+485
git://anongit.freedesktop.org/tegra/linux into drm-next drm/tegra: Changes for v4.8-rc1 This set of changes contains a bunch of cleanups to the host1x driver as well as the addition of a pin controller for DPAUX, which is required by boards to configure the DPAUX pads in AUX mode (for DisplayPort) or I2C mode (for HDMI and DDC). Included is also a bit of rework of the SOR driver in preparation to add DisplayPort support as well as some refactoring and cleanup. Finally, all output drivers are converted to runtime PM, which greatly simplifies the handling of clocks and resets. * tag 'drm/tegra/for-4.8-rc1' of git://anongit.freedesktop.org/tegra/linux: (35 commits) drm/tegra: sor: Reject HDMI 2.0 modes drm/tegra: sor: Prepare for generic PM domain support drm/tegra: dsi: Prepare for generic PM domain support drm/tegra: sor: Make XBAR configurable per SoC drm/tegra: sor: Use sor1_src clock to set parent for HDMI dt-bindings: display: tegra: Add source clock for SOR drm/tegra: sor: Implement sor1_brick clock drm/tegra: sor: Implement runtime PM drm/tegra: hdmi: Implement runtime PM drm/tegra: dsi: Implement runtime PM drm/tegra: dc: Implement runtime PM drm/tegra: hdmi: Enable audio over HDMI drm/tegra: sor: Do not support deep color modes drm/tegra: sor: Extract tegra_sor_mode_set() drm/tegra: sor: Split out tegra_sor_apply_config() drm/tegra: sor: Rename tegra_sor_calc_config() drm/tegra: sor: Factor out tegra_sor_set_parent_clock() drm/tegra: dpaux: Add pinctrl support dt-bindings: Add bindings for Tegra DPAUX pinctrl driver drm/tegra: Prepare DPAUX for supporting generic PM domains ...
2016-07-14drm/tegra: sor: Reject HDMI 2.0 modesThierry Reding1-0/+4
Enabling HDMI 2.0 modes requires extra programming and will not work with the current driver, so reject all those modes. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14drm/tegra: sor: Prepare for generic PM domain supportJon Hunter1-22/+35
The SOR driver for Tegra requires the SOR power partition to be enabled. Now that Tegra supports the generic PM domain framework we manage the SOR power partition via this framework. However, the sequence for gating/ungating the SOR power partition requires that the SOR reset is asserted/de-asserted at the time the SOR power partition is gated/ungated, respectively. Now that the reset control core assumes that resets are exclusive, the Tegra generic PM domain code and the SOR driver cannot request the same reset unless we mark the reset as shared. Sharing resets will not work in this case because we cannot guarantee that the reset will be asserted/de-asserted at the appropriate time. Therefore, given that the Tegra generic PM domain code will handle the resets, do not request the reset in the SOR driver if the SOR device has a PM domain associated. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14drm/tegra: sor: Make XBAR configurable per SoCThierry Reding1-13/+28
Provide a per-SoC mapping of lanes which can be used to configure the XBAR. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14drm/tegra: sor: Use sor1_src clock to set parent for HDMIThierry Reding1-1/+16
When running in HDMI mode, the sor1 IP block needs to use the sor1_src as parent clock, and in turn configure the sor1_src to use pll_d2_out0 as its parent. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-14drm/tegra: sor: Implement sor1_brick clockThierry Reding1-0/+107
sor1_brick is a clock that can be used as a source for the sor1 clock. The registers to control the clock output are part of the sor1 IP block and hence the sor driver is the best place to implement it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-04drm/tegra: sor: Implement runtime PMThierry Reding1-19/+58
Use runtime PM to clock-(un)gate and (de)assert reset to the SOR controller. This ties in nicely with atomic DPMS in that a runtime PM reference is taken before a pipe is enabled and dropped after it has been shut down. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-04drm/tegra: sor: Do not support deep color modesThierry Reding1-14/+86
Current generations of Tegra do not support deep color modes, so force 8 bits per color even if the connected monitor or panel supports more. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-04drm/tegra: sor: Extract tegra_sor_mode_set()Thierry Reding1-133/+93
The code to set a video mode is common to all types of outputs that the SOR can drive. Extract it into a separate function so that it can be shared. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-01drm/tegra: sor: Split out tegra_sor_apply_config()Thierry Reding1-34/+43
This function is useful in both eDP and DP modes, so split it out in anticipation of adding DP support. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-01drm/tegra: sor: Rename tegra_sor_calc_config()Thierry Reding1-7/+6
Use a slightly more sensible name, tegra_sor_compute_config(). Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-01drm/tegra: sor: Factor out tegra_sor_set_parent_clock()Thierry Reding1-7/+28
Switching the SOR parent clock can glitch if done while the clock is enabled. Extract a common function that can be used to disable the module clock, switch the parent and reenable the module clock. Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-10drm: tegra: Rely on the default ->best_encoder() behaviorBoris Brezillon1-1/+0
All outputs have a 1:1 relationship between connectors and encoders and the driver is relying on the atomic helpers: we can drop the custom ->best_encoder() implementation and let the core call drm_atomic_helper_best_encoder() for us. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1465300095-16971-14-git-send-email-boris.brezillon@free-electrons.com
2015-12-17Merge tag 'drm/tegra/for-4.5-rc1' of ↵Dave Airlie1-80/+65
git://anongit.freedesktop.org/tegra/linux into drm-next drm/tegra: Changes for v4.5-rc1 This adds support for the version of host1x found on Tegra210 SoCs. It also makes use of the new atomic suspend/resume functionality to bring this feature to Tegra. Other than that it's mostly small fixes and cleanups, with some prep- work for things that will hopefully get merged for the next release. * tag 'drm/tegra/for-4.5-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/tegra: Advertise DRIVER_ATOMIC drm/tegra: Use DRIVER level for IOMMU aperture message drm/tegra: checking for IS_ERR() instead of NULL drm/tegra: dc: Add missing of_node_put() drm/tegra: Implement subsystem-level suspend/resume drm/tegra: sor: Remove unnecessary conditional drm/tegra: sor: Operate on struct drm_dp_aux * drm/tegra: Use drm_gem_object_unreference_unlocked() drm/tegra: Don't take dev->struct_mutex in mmap offset ioctl drm/tegra: Use unlocked gem unreferencing drm/tegra: Use new multi-driver module helpers gpu: host1x: Add Tegra210 support gpu: host1x: Remove core driver on unregister gpu: host1x: Use platform_register/unregister_drivers()
2015-12-14drm/tegra: checking for IS_ERR() instead of NULLDan Carpenter1-3/+3
The tegra_sor_hdmi_find_settings() function returns NULL on error and not an ERR_PTR. Fixes: 459cc2c6800b ('drm/tegra: sor: Add HDMI support') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-14drm/tegra: sor: Remove unnecessary conditionalThierry Reding1-52/+41
Checking for sor->aux in eDP specific code is unnecessary because eDP inherently requires a valid AUX channel. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-14drm/tegra: sor: Operate on struct drm_dp_aux *Thierry Reding1-32/+28
Instead of getting a pointer to the driver-specific wrapper of AUX channels, use the AUX channel objects directly to avoid hackish casting between the two types. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-11drm: Pass 'name' to drm_encoder_init()Ville Syrjälä1-1/+1
Done with coccinelle for the most part. However, it thinks '...' is part of the semantic patch, so I put an 'int DOTDOTDOT' placeholder in its place and got rid of it with sed afterwards. @@ identifier dev, encoder, funcs; @@ int drm_encoder_init(struct drm_device *dev, struct drm_encoder *encoder, const struct drm_encoder_funcs *funcs, int encoder_type + ,const char *name, int DOTDOTDOT ) { ... } @@ identifier dev, encoder, funcs; @@ int drm_encoder_init(struct drm_device *dev, struct drm_encoder *encoder, const struct drm_encoder_funcs *funcs, int encoder_type + ,const char *name, int DOTDOTDOT ); @@ expression E1, E2, E3, E4; @@ drm_encoder_init(E1, E2, E3, E4 + ,NULL ) v2: Add ', or NULL...' to @name kernel doc (Jani) Annotate the function with __printf() attribute (Jani) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1449670818-2966-1-git-send-email-ville.syrjala@linux.intel.com
2015-11-09remove abs64()Andrew Morton1-2/+2
Switch everything to the new and more capable implementation of abs(). Mainly to give the new abs() a bit of a workout. Cc: Michal Nazarewicz <mina86@mina86.com> Cc: John Stultz <john.stultz@linaro.org> Cc: Ingo Molnar <mingo@kernel.org> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2015-08-13drm/tegra: sor: Add HDMI supportThierry Reding1-34/+960
The SOR1 introduced on Tegra210 supports HDMI 2.0 and DisplayPort. Add HDMI support and name the debugfs node after the type of SOR. The SOR introduced with Tegra124 is known simply as "sor", whereas the additional SOR found on Tegra210 is known as "sor1". Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13drm/tegra: sor: Add Tegra210 eDP supportThierry Reding1-0/+1
The SOR found on Tegra210 is very similar to the version found on Tegra124, except that it no longer supports LVDS. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13drm/tegra: sor: Restore DPMSThierry Reding1-138/+82
In order to restore DPMS with atomic mode-setting, move all code from the ->mode_set() callback into ->enable(). At the same time, rename the ->prepare() callback to ->disable() to use the names preferred by atomic mode-setting. This simplifies the calling sequence and will allow DPMS to use runtime PM in subsequent patches. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13drm/tegra: sor: Use DRM debugfs infrastructure for CRCThierry Reding1-37/+8
Instead of duplicating most of the code to set up a debugfs file, use the existing DRM core debugfs infrastructure instead. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13drm/tegra: sor: Write correct head state registersThierry Reding1-4/+6
The head state registers are per head, so they must be properly indexed. This has worked fine so far because all boards with eDP use it as the primary output, so it is very likely to end up attached to head 0. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13drm/tegra: sor: Constify display modeThierry Reding1-1/+1
The data structure is always only read, never written, and can hence be referred to by a const pointer. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13drm/tegra: sor: Reset the correct debugfs fieldsThierry Reding1-2/+2
When tearing down debugfs support, make sure to reset the fields to NULL in the correct order, otherwise the debugfs root will not be properly removed. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13drm/tegra: sor: Set minor after debugfs initializationThierry Reding1-0/+2
The DRM minor is needed to teardown debugfs, so it needs to be tracked to prevent a crash on driver removal. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13drm/tegra: sor: Provide error messages in probeThierry Reding1-6/+23
When probing the SOR device fails, output proper error messages to help diagnose the cause of the failure. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13drm/tegra: sor: Rename registers for consistencyThierry Reding1-186/+185
The TRM lists indexed registers without an underscore to separate name from index. Use that convention in the driver for consistency. While at it, rename some of the field names to the names used in the TRM. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: sor: Reset during initializationTomeu Vizoso1-0/+18
As there isn't a way for the firmware on the Nyan Chromebooks to hand over the display to the kernel, and the kernel isn't redoing the whole configuration at present. With this patch, the SOR is brought to a known state and we get correct display on every boot. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: sor: Dump registers via debugfsThierry Reding1-6/+165
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02drm/tegra: sor: Registers are 32-bitThierry Reding1-7/+6
Use a sized unsigned 32-bit data type (u32) to store register contents. The SOR registers are 32 bits wide irrespective of the architecture's data width. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-27drm/tegra: dc: Unify enabling the display controllerThierry Reding1-22/+3
Previously output drivers would enable continuous display mode and power up the display controller at various points during the initialization. This is suboptimal because it accesses display controller registers in output drivers and duplicates a bit of code. Move this code into the display controller driver and enable the display controller as the final step of the ->mode_set_nofb() implementation. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-27drm/tegra: Remove unused ->mode_fixup() callbacksThierry Reding1-27/+0
All output drivers have now been converted to use the ->atomic_check() callback, so the ->mode_fixup() callbacks are no longer used. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-27drm/tegra: sor: Implement ->atomic_check()Thierry Reding1-0/+22
The implementation of the ->atomic_check() callback precomputes all parameters to check if the given configuration can be applied. If so the precomputed values are stored in the atomic state object for the encoder and applied during modeset. In that way the modeset no longer needs to perform any checking but simply program values into registers. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-27drm/tegra: Atomic conversion, phase 2Thierry Reding1-0/+2
Hook up the default ->reset() and ->atomic_duplicate_state() helpers. This ensures that state objects are properly created and framebuffer reference counts correctly maintained. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-27drm/tegra: Atomic conversion, phase 1Thierry Reding1-0/+2
Implement initial atomic state handling. Hook up the CRTCs, planes' and connectors' ->atomic_destroy_state() callback to ensure that the atomic state objects don't leak. Furthermore the CRTC now implements the ->mode_set_nofb() callback that is used by new helpers to implement ->mode_set() and ->mode_set_base(). These new helpers also make use of the new plane helper functions which the driver now provides. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-27drm/tegra: Output cleanup functions cannot failThierry Reding1-5/+3
The tegra_output_exit() and tegra_output_remove() functions cannot fail, so make them return void. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-27drm/tegra: Remove remnants of the output midlayerThierry Reding1-6/+6
The tegra_output midlayer is now completely gone and output drivers use it purely as a helper library. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-27drm/tegra: debugfs cleanup cannot failThierry Reding1-8/+3
The debugfs cleanup code never fails, so no error is returned. Therefore the functions can all return void instead. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-27drm/tegra: sor: DemidlayerThierry Reding1-350/+408
Implement encoder and connector within the eDP driver itself using the Tegra output helpers rather than using the Tegra output as midlayer. By doing so one level of indirection is removed and output drivers become more flexible while keeping the majority of the advantages provided by the common output helpers. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-27drm/tegra: Stop CRTC at CRTC disable timeThierry Reding1-4/+0
Previously output drivers would all stop the display controller in their disable path. However with the transition to atomic modesetting the display controller needs to be kept running until all planes have been disabled so that software can properly determine (using VBLANK counts) when it is safe to remove the framebuffers associated with the planes. Moving this code into the display controller's disable path also gets rid of the duplication of this into all output drivers. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-27drm/tegra: Use tegra_commit_dc() in output driversThierry Reding1-4/+2
All output drivers have open-coded variants of this function, so export it to remove some code duplication. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-08-08Merge tag 'cleanup-for-3.17' of ↵Linus Torvalds1-1/+2
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC cleanups from Olof Johansson: "This merge window brings a good size of cleanups on various platforms. Among the bigger ones: - Removal of Samsung s5pc100 and s5p64xx platforms. Both of these have lacked active support for quite a while, and after asking around nobody showed interest in keeping them around. If needed, they could be resurrected in the future but it's more likely that we would prefer reintroduction of them as DT and multiplatform-enabled platforms instead. - OMAP4 controller code register define diet. They defined a lot of registers that were never actually used, etc. - Move of some of the Tegra platform code (PMC, APBIO, fuse, powergate) to drivers/soc so it can be shared with 64-bit code. This also converts them over to traditional driver models where possible. - Removal of legacy gpio-samsung driver, since the last users have been removed (moved to pinctrl) Plus a bunch of smaller changes for various platforms that sort of dissapear in the diffstat for the above. clps711x cleanups, shmobile header file refactoring/moves for multiplatform friendliness, some misc cleanups, etc" * tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (117 commits) drivers: CCI: Correct use of ! and & video: clcd-versatile: Depend on ARM video: fix up versatile CLCD helper move MAINTAINERS: Add sdhci-st file to ARCH/STI architecture ARM: EXYNOS: Fix build breakge with PM_SLEEP=n MAINTAINERS: Remove Kirkwood ARM: tegra: Convert PMC to a driver soc/tegra: fuse: Set up in early initcall ARM: tegra: Always lock the CPU reset vector ARM: tegra: Setup CPU hotplug in a pure initcall soc/tegra: Implement runtime check for Tegra SoCs soc/tegra: fuse: fix dummy functions soc/tegra: fuse: move APB DMA into Tegra20 fuse driver soc/tegra: Add efuse and apbmisc bindings soc/tegra: Add efuse driver for Tegra ARM: tegra: move fuse exports to soc/tegra/fuse.h ARM: tegra: export apb dma readl/writel ARM: tegra: Use a function to get the chip ID ARM: tegra: Sort includes alphabetically ARM: tegra: Move includes to include/soc/tegra ...
2014-08-04drm/tegra: add MODULE_DEVICE_TABLEsStephen Warren1-0/+1
When tegra-drm.ko is built as a module, these MODULE_DEVICE_TABLEs allow the module to be auto-loaded since the module will match the devices instantiated from device tree. (Notes for stable: in 3.14+, just git rm any conflicting file, since they are added in later kernels. For 3.13 and below, manual merging will be needed) Cc: <stable@vger.kernel.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-08-04drm/tegra: sor - Configure proper sync polaritiesThierry Reding1-3/+13
Program the sync signal polarities according to the display mode. Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-08-04drm/tegra: sor - Use bits-per-color from panelStéphane Marchesin1-1/+1
This change uses the value of bits-per-color from panel to remove one more hardcoded value. Signed-off-by: Stéphane Marchesin <marcheu@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-08-04drm/tegra: sor - missing unlock on errorDan Carpenter1-1/+1
We should unlock before returning the error code. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17ARM: tegra: Convert PMC to a driverThierry Reding1-1/+1
This commit converts the PMC support code to a platform driver. Because the boot process needs to call into this driver very early, also set up a minimal environment via an early initcall. Signed-off-by: Thierry Reding <treding@nvidia.com>
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