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path: root/drivers/gpu/drm/radeon/rs400.c
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2017-03-29gpu: drm: amd/radeon: Convert printk(KERN_<LEVEL> to pr_<level>Joe Perches1-2/+2
Use a more common logging style. Miscellanea: o Coalesce formats and realign arguments o Neaten a few macros now using pr_<level> Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-01-22drm/radeon: Split off gart_get_page_entry ASIC hook from set_page_entryMichel Dänzer1-5/+9
get_page_entry calculates the GART page table entry, which is just written to the GART page table by set_page_entry. This is a prerequisite for the following fix. Reviewed-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-09-18drm/radeon: Fix typo 'addr' -> 'entry' in rs400_gart_set_pageMichel Dänzer1-2/+2
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83996 Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: Pass GART page flags to radeon_gart_set_page() explicitlyMichel Dänzer1-3/+10
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-05drm/radeon: Remove radeon_gart_restore()Michel Dänzer1-1/+0
Doesn't seem necessary, the GART table memory should be persistent. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-06-09drm/radeon: remove range check from *_gart_set_pageChristian König1-6/+1
We never check the return value anyway and if the index isn't valid would crash way before calling the functions. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-03-06drm/radeon: resume old pm lateAlex Deucher1-2/+0
Moving the pm resume up in the init order to fix dpm seems to have regressed somes cases with the old pm code. Move it back to late resume. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-12-24drm/radeon/pm: move pm handling into the asic specific codeAlex Deucher1-0/+7
We need more control over the ordering of dpm init with respect to the rest of the asic. Specifically, the SMC has to be initialized before the rlc and cg/pg. The pm code currently initializes late in the driver, but we need it to happen much earlier so move pm handling into the asic specific callbacks. This makes dpm more reliable and makes clockgating work properly on CIK parts and should help on SI parts as well. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-11drm/radeon: add spinlocks for indirect register accesssAlex Deucher1-0/+7
This adds spinlocks to protect access to other indirect register apertures. These indirect spaces are used pretty infrequently and we haven't had an reported problems, but better safe than sorry. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30drm/radeon: fix resume on some rs4xx boards (v2)Alex Deucher1-3/+6
Setting MC_MISC_CNTL.GART_INDEX_REG_EN causes hangs on some boards on resume. The systems seem to work fine without touching this bit so leave it as is. v2: read-modify-write the GART_INDEX_REG_EN bit. I suspect the problem is that we are losing the other settings in the register. fixes: https://bugs.freedesktop.org/show_bug.cgi?id=52952 Reported-by: Ondrej Zary <linux@rainbow-software.org> Tested-by: Daniel Tobias <dan.g.tob@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2013-06-03radeon: Fix system hang issue when using KMS with older cardsAdis Hamzić1-3/+6
The current radeon driver initialization routines, when using KMS, are written so that the IRQ installation routine is called before initializing the WB buffer and the CP rings. With some ASICs, though, the IRQ routine tries to access the GFX_INDEX ring causing a call to RREG32 with the value of -1 in radeon_fence_read. This, in turn causes the system to completely hang with some cards, requiring a hard reset. A call stack that can cause such a hang looks like this (using rv515 ASIC for the example here): * rv515_init (rv515.c) * radeon_irq_kms_init (radeon_irq_kms.c) * drm_irq_install (drm_irq.c) * radeon_driver_irq_preinstall_kms (radeon_irq_kms.c) * rs600_irq_process (rs600.c) * radeon_fence_process - due to SW interrupt (radeon_fence.c) * radeon_fence_read (radeon_fence.c) * hang due to RREG32(-1) The patch moves the IRQ installation to the card startup routine, after the ring has been initialized, but before the IRQ has been set. This fixes the issue, but requires a check to see if the IRQ is already installed, as is the case in the system resume codepath. I have tested the patch on three machines using the rv515, the rv770 and the evergreen ASIC. They worked without issues. This seems to be a known issue and has been reported on several bug tracking sites by various distributions (see links below). Most of reports recommend booting the system with KMS disabled and then enabling KMS by reloading the radeon module. For some reason, this was indeed a usable workaround, however, UMS is now deprecated and disabled by default. Bug reports: https://bugzilla.redhat.com/show_bug.cgi?id=845745 https://bugs.launchpad.net/ubuntu/+source/linux/+bug/561789 https://bbs.archlinux.org/viewtopic.php?id=156964 Signed-off-by: Adis Hamzić <adis@hamzadis.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2012-09-20drm/radeon: Mark all possible functions / structs as staticLauri Kasanen1-3/+3
Let's allow GCC to optimize better. This exposed some five unused functions, but this patch doesn't remove them. Signed-off-by: Lauri Kasanen <cand@gmx.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-17drm/radeon: move radeon_ib_ring_tests out of chipset codeChristian König1-4/+0
Making it easier to control when it is executed. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-17drm/radeon: remove ip_pool start/suspendChristian König1-11/+6
The IB pool is in gart memory, so it is completely superfluous to unpin / repin it on suspend / resume. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-05-03drm/radeon: use central function for IB testingChristian König1-5/+2
Removing all the different error messages and having just one standard behaviour over all chipset generations. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-03-15drm: Merge tag 'v3.3-rc7' into drm-core-nextDave Airlie1-1/+7
Merge the fixes so far into core-next, needed to test intel driver. Conflicts: drivers/gpu/drm/i915/intel_ringbuffer.c
2012-02-29drm/radeon/kms: make ring_start, ring_test, and ib_test per ringAlex Deucher1-1/+1
Each ring type may need a different variant. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König<christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-02-22drm/radeon/kms: properly set accel working flag and bailout when falseJerome Glisse1-1/+7
If accel is not working many subsystem such as the ib pool might not be initialized properly that can lead to segfault inside kernel when cs ioctl is call with non working acceleration. To avoid this make sure the accel working flag is false when an error in GPU startup happen and return EBUSY from cs ioctl if accel is not working. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-12-20drm/radeon: introduce a sub allocator and convert ib pool to it v4Jerome Glisse1-2/+19
Somewhat specializaed sub-allocator designed to perform sub-allocation for command buffer not only for current cs ioctl but for future command submission ioctl as well. Patch also convert current ib pool to use the sub allocator. Idea is that ib poll buffer can be share with other command buffer submission not having 64K granularity. v2 Harmonize pool handling and add suspend/resume callback to pin/unpin sa bo (tested on rv280, rv370, r420, rv515, rv610, rv710, redwood, cayman, rs480, rs690, rs880) v3 Simplify allocator v4 Fix radeon_ib_get error path to properly free fence Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-12-20drm/radeon: precompute fence cpu/gpu addr once v3Jerome Glisse1-1/+7
Add a start fence driver helper function which will be call once for each ring and will compute cpu/gpu addr for fence depending on wether to use wb buffer or scratch reg. This patch replace initialize fence driver separately which was broken in regard of GPU lockup. The fence list for created, emited, signaled must be initialize once and only from the asic init callback not from the startup call back which is call from the gpu reset. v2: With this in place we no longer need to know the number of rings in fence_driver_init, also writing to the scratch reg before knowing its offset is a bad idea. v3: rebase on top of change to previous patch in the serie Signed-off-by: Christian König <deathsimple@vodafone.de> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-12-20drm/radeon/kms: add support for multiple fence queues v2Alex Deucher1-1/+1
For supporting multiple CP ring buffers, async DMA engines and UVD. We still need a way to synchronize between engines. v2 initialize unused fence driver ring to avoid issue in suspend/unload Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-04drm/radeon/kms: consolidate GART code, fix segfault after GPU lockup V2Jerome Glisse1-2/+3
After GPU lockup VRAM gart table is unpinned and thus its pointer becomes unvalid. This patch move the unpin code to a common helper function and set pointer to NULL so that page update code can check if it should update GPU page table or not. That way bo still bound to GART can be unbound (pci_unmap_page for all there page) properly while there is no need to update the GPU page table. V2 move the test for null gart out of the loop, small optimization Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-09-06drm/radeon: Print gart initialization details on all chipsetsTormod Volden1-0/+3
This was previously done for r300 only. Use %016llX instead of %08X for printing the table address. Also fix typos in gart warning messages. Signed-off-by: Tormod Volden <debian.tormod@gmail.com> Reviewed-by: Michel Dänzer <michel@daenzer.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-17drm: Fix printk typo 'failled'Paul Bolle1-2/+2
Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2011-01-27drm/radeon/kms: clean up some magic numbersAlex Deucher1-6/+9
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@gmail.com>
2010-11-09drivers/gpu/drm: Update WARN usesJoe Perches1-1/+1
Coalesce long formats. Align arguments. Add missing newlines. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-10-06drm/radeon/kms: enable writeback (v2)Alex Deucher1-6/+9
When writeback is enabled, the GPU shadows writes to certain registers into a buffer in memory. The driver can then read the values from the shadow rather than reading back from the register across the bus. Writeback can be disabled by setting the no_wb module param to 1. On r6xx/r7xx/evergreen, the following registers are shadowed: - CP scratch registers - CP read pointer - IH write pointer On r1xx-rr5xx, the following registers are shadowed: - CP scratch registers - CP read pointer v2: - Combine wb patches for r6xx-evergreen and r1xx-r5xx - Writeback is disabled on AGP boards since it tends to be unreliable on AGP using the gart. - Check radeon_wb_init return values properly. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-08-02drm/radeon/kms: remove rs4xx gart limitAlex Deucher1-8/+0
We used to limit the rs4xx gart aperture to 32 MB, but I suspect that was due to not meeting the alignment requirements of the aperture. This patch should only be applied after: "drm/radeon/kms: fix gtt MC base alignment on rs4xx/rs690/rs740 asics" has been applied. This patch should probably soak for a bit in d-r-t. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-08-02Merge tag 'v2.6.35-rc6' into drm-radeon-nextDave Airlie1-1/+4
Need this to avoid conflicts with future radeon fixes
2010-08-02drm/radeon/kms: check/restore sanity before doing anything else with GPU.Dave Airlie1-0/+2
On systems using kexec, the new kernel is booted straight from the old kernel, without any warning to the graphics driver. So the GPU is basically left as-is in a running state, however the CPU side is completly reset. Without stating the saneness of anyone using kexec on live systems, we should at least try not to crash the GPU. This patch resets 3 registers to 0 that could cause bad things to happen to the running system. This allows kexec to work on a Power6/RN50 system. Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-07-16drm/radeon/kms: fix gtt MC base alignment on rs4xx/rs690/rs740 asicsAlex Deucher1-1/+4
The asics in question have the following requirements with regard to their gart setups: 1. The GART aperture size has to be in the form of 2^X bytes, where X is from 25 to 31 2. The GART aperture MC base has to be aligned to a boundary equal to the size of the aperture. 3. The GART page table has to be aligned to the boundary equal to the size of the table. 4. The GART page table size is: table_entry_size * (aperture_size / page_size) 5. The GART page table has to be allocated in non-paged, non-cached, contiguous system memory. This patch takes care 2. The rest should already be handled properly. This fixes a regression noticed by: Torsten Kaiser <just.for.lkml@googlemail.com> Tested-by: Torsten Kaiser <just.for.lkml@googlemail.com> Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-05-18drm/radeon/kms/pm: rework power managementAlex Deucher1-3/+0
- Separate dynpm and profile based power management methods. You can select the pm method by echoing the selected method ("dynpm" or "profile") to power_method in sysfs. - Expose basic 4 profile in profile method "default" - default clocks "auto" - select between low and high based on ac/dc state "low" - DC, low power mode "high" - AC, performance mode The current base profile is "default", but it should switched to "auto" once we've tested on more systems. Switching the state is a matter of echoing the requested profile to power_profile in sysfs. The lowest power states are selected automatically when dpms turns the monitors off in all states but default. - Remove dynamic fence-based reclocking for the moment. We can revisit this later once we have basic pm in. - Move pm init/fini to modesetting path. pm is tightly coupled with display state. Make sure display side is initialized before pm. - Add pm suspend/resume functions to make sure pm state is properly reinitialized on resume. - Remove dynpm module option. It's now selectable via sysfs. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-04-20Merge branch 'drm-radeon-lockup' into drm-core-nextDave Airlie1-4/+2
* drm-radeon-lockup: drm/radeon/kms: simplify & improve GPU reset V2 drm/radeon/kms: rename gpu_reset to asic_reset drm/radeon/kms: fence cleanup + more reliable GPU lockup detection V4 Conflicts: drivers/gpu/drm/radeon/r300.c
2010-04-06drm/radeon/kms: simplify & improve GPU reset V2Jerome Glisse1-2/+0
This simplify and improve GPU reset for R1XX-R6XX hw, it's not 100% reliable here are result: - R1XX/R2XX works bunch of time in a row, sometimes it seems it can work indifinitly - R3XX/R3XX the most unreliable one, sometimes you will be able to reset few times, sometimes not even once - R5XX more reliable than previous hw, seems to work most of the times but once in a while it fails for no obvious reasons (same status than previous reset just no same happy ending) - R6XX/R7XX are lot more reliable with this patch, still it seems that it can fail after a bunch (reset every 2sec for 3hour bring down the GPU & computer) This have been tested on various hw, for some odd reasons i wasn't able to lockup RS480/RS690 (while they use to love locking up). Note that on R1XX-R5XX the cursor will disapear after lockup haven't checked why, switch to console and back to X will restore cursor. Next step is to record the bogus command that leaded to the lockup. V2 Fix r6xx resume path to avoid reinitializing blit module, use the gpu_lockup boolean to avoid entering inifinite waiting loop on fence while reiniting the GPU Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-04-06drm/radeon/kms: rename gpu_reset to asic_resetJerome Glisse1-2/+2
Patch rename gpu_reset to asic_reset in prevision of having gpu_reset doing more stuff than just basic asic reset. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-04-05Merge branch 'master' into export-slabhTejun Heo1-1/+6
2010-04-01drm/radeon/kms: rs400/480 should set common registers.Dave Airlie1-0/+2
These GPUs should be setting these registers up also. Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-03-31drm/radeon/kms: avoid possible oops (call gart_fini before gart_disable)Jerome Glisse1-1/+1
radeon_gart_fini might call GART unbind callback function which might try to access GART table but if gart_disable is call first the GART table will be unmapped so any access to it will oops. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-03-31drm/radeon/kms: fix display bandwidth setup on rs4xxAlex Deucher1-0/+1
I missed rs4xx in 7f1e613daf0fdd0884316ab25a749db3c671329e Fixes fdo bug 27219. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-03-31drm/radeon/kms: expose thermal/fan i2c busesAlex Deucher1-0/+1
Look up i2c bus in the power table and expose it. You'll need to load a hwmon driver for any chips on the bus, this patch just exposes the bus. Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2010-03-30include cleanup: Update gfp.h and slab.h includes to prepare for breaking ↵Tejun Heo1-0/+1
implicit slab.h inclusion from percpu.h percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-15drm/radeon: include radeon_asic.h in the asic specific filesDaniel Vetter1-0/+1
In essence this creates a home for all asic specific declarations in radeon_asic.h Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-18drm/radeon/kms: simplify memory controller setup V2Jerome Glisse1-27/+11
Get rid of _location and use _start/_end also simplify the computation of vram_start|end & gtt_start|end. For R1XX-R2XX we place VRAM at the same address of PCI aperture, those GPU shouldn't have much memory and seems to behave better when setup that way. For R3XX and newer we place VRAM at 0. For R6XX-R7XX AGP we place VRAM before or after AGP aperture this might limit to limit the VRAM size but it's very unlikely. For IGP we don't change the VRAM placement. Tested on (compiz,quake3,suspend/resume): PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710 AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730 IGP:RS480(RPB*),RS690,RS780(RPB*),RS880 RPB: resume previously broken V2 correct commit message to reflect more accurately the bug and move VRAM placement to 0 for most of the GPU to avoid limiting VRAM. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-11drm/radeon/kms: set gart pages to invalid on unbind and point to dummy pageDave Airlie1-0/+1
this uses a new entrypoint to invalidate gart entries instead of using 0. Changed to rather than pointing to 0 address point empty entry to dummy page. This might help to avoid hard lockup if for some wrong reasons GPU try to access unmapped GART entry. I'm not 100% sure this is going to work, we probably need to allocate a dummy page and point all the GTT entries at it similiar to what AGP does. but we can test this first I suppose. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-05drm/radeon/kms: rs400/480 MC setup is different than r300.Dave Airlie1-5/+21
Boot testing on my rs480 laptop found the MC idle never happened on startup, a quick check with AMD found the idle bit is in a different place on the rs4xx than r300. Implement a new rs400 mc idle function to fix this. Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-05drm/radeon/kms: don't call suspend path before cleaning up GPUJerome Glisse1-2/+0
In suspend path we unmap the GART table while in cleaning up path we will unbind buffer and thus try to write to unmapped GART leading to oops. In order to avoid this we don't call the suspend path in cleanup path. Cleanup path is clever enough to desactive GPU like the suspend path is doing, thus this was redondant. Tested on: RV370, R420, RV515, RV570, RV610, RV770 (all PCIE) Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-01-08drm/radeon/kms: Schedule host path read cache flush through the ring V2Jerome Glisse1-0/+1
R300 family will hard lockup if host path read cache flush is done through MMIO to HOST_PATH_CNTL. But scheduling same flush through ring seems harmless. This patch remove the hdp_flush callback and add a flush after each fence emission which means a flush after each IB schedule. Thus we should have same behavior without the hard lockup. Tested on R100,R200,R300,R400,R500,R600,R700 family. V2: Adjust fence counts in r600_blit_prepare_copy() Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-01-08drm/radeon/kms: detect sideport memory on IGP chipsAlex Deucher1-0/+1
This detects if the sideport memory is enabled and if it is VRAM is evicted on suspend/resume. This should fix s/r issues on some IGPs. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-12-16drm/radeon/kms: init pm on all chipsetsRafał Miłecki1-0/+2
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-12-10drm/radeon/kms: restore surface registers on resume.Dave Airlie1-0/+2
On resume on my rv530 laptop surface cntl was left disabled, so wierd stuff would happen with rendering to a tiled front buffer. This checks if the surface regs are assigned to bos and reprograms the surface registers on resume using the same path that clears them all on init. Signed-off-by: Dave Airlie <airlied@redhat.com>
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