summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/radeon/atombios_crtc.c
AgeCommit message (Collapse)AuthorFilesLines
2012-04-27drm/radeon/kms: use frac fb div on APUsAlex Deucher1-0/+3
Seems to be more stable on certain monitors. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=48880 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-04-24drm/radeon/kms: improve bpc handling (v2)Alex Deucher1-5/+2
Improve handling of bpc (bits per color) in radeon. In most cases we want 8 except for HDMI, DP, LVDS, and eDP. v2: handle DP better. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Tested-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-03-26drm/radeon/kms/atom: force bpc to 8 for nowAlex Deucher1-3/+5
Using the bpc (bits per color) specified by the monitor can cause problems in some cases. Until we get a better handle on how to deal with those cases, just use a bpc of 8. Reported-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-03-21drm/radeon/kms/DCE6.1: ss is not supported on the internal ppllsAlex Deucher1-1/+1
It's handled via external clock. It should already be protected by the external ss flag, but add an explicit check just in case. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-03-21drm/radeon/kms: disable PPLL0 on DCE6.1 when not in useAlex Deucher1-0/+8
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-03-21drm/radeon/kms: Adjust pll picker for DCE6.1Alex Deucher1-1/+30
On TN, UNIPHYA always uses PPLL2, UNIPHYB/C/D/E/F can use either PPLL1 or PPLL0. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-03-21drm/radeon/kms: DCE6.1 disp eng pll updatesAlex Deucher1-1/+3
DCE6.1 uses EXT_PLL1 for disp eng. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-03-21drm/radeon/kms: DCE6 disp eng pll updatesAlex Deucher1-5/+10
Rename the function to better match the functionality. DCPLL became PLL0 on DCE6. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-03-21drm/radeon/kms/atom: add support for crtc power gatingAlex Deucher1-0/+38
Each pair of crtcs (0/1, 2/3, 4/5) can be power gated. Make sure the power is applied when the crtc is in use and only power down the pair when both are off. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-03-21drm/radeon/kms/atom: DCE6 no longer has crtcmemreq bitsAlex Deucher1-2/+2
The hw no longer has the bits and the table is removed. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-02-13drm/radeon: add support for evergreen/ni tiling informations v11Jerome Glisse1-13/+7
evergreen and northern island gpu needs more informations for 2D tiling than previous r6xx/r7xx. Add field to tiling ioctl to allow userspace to provide those. The v8 cs checking change to track color view on r6xx/r7xx doesn't affect old userspace as old userspace always emited 0 for this register. v2 fix r6xx/r7xx 2D tiling computation v3 fix r6xx/r7xx height align for untiled surface & add support for tile split on evergreen and newer v4 improve tiling debugging output v5 fix tile split code for evergreen and newer v6 set proper tile split for crtc register v7 fix tile split limit value v8 add COLOR_VIEW checking to r6xx/r7xx checker, add evergreen cs checking, update safe reg for r600, evergreen and cayman. Evergreen checking need some work around for stencil alignment issues v9 fix tile split value range, fix compressed texture handling and mipmap calculation, allow evergreen check to be silencious in front of current broken userspace (depth/stencil alignment issue) v10 fix eg 3d texture and compressed texture, fix r600 depth array, fix r600 color view computation, add support for evergreen stencil split v11 more verbose debugging in some case Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-02-01drm/radeon: Set DESKTOP_HEIGHT register to the framebuffer (not mode) height.Michel Dänzer1-2/+2
The value of this register is transferred to the V_COUNTER register at the beginning of vertical blank. V_COUNTER is the reference for VLINE waits and goes from VIEWPORT_Y_START to VIEWPORT_Y_START+VIEWPORT_HEIGHT during scanout, so if VIEWPORT_Y_START is not 0, V_COUNTER actually went backwards at the beginning of vertical blank, and VLINE waits excluding the whole scanout area could never finish (possibly only if VIEWPORT_Y_START is larger than the length of vertical blank in scanlines). Setting DESKTOP_HEIGHT to the framebuffer height should prevent this for any kind of VLINE wait. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=45329 . CC: stable@vger.kernel.org Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-24drm/radeon/kms: refine TMDS dual link checksAlex Deucher1-1/+3
HDMI 1.3 defines single link clocks up to 340 Mhz. Refine the current dual link checks to only enable dual link for DVI > 165 Mhz or HDMI > 340 Mhz if the hw supports HDMI 1.3 (DCE3+). Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=44755 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-24drm/radeon/kms: move disp eng pll setup to init pathAlex Deucher1-29/+27
We really only need to set it up once on init or resume rather than on every mode set. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-12-20drm/radeon/kms: don't use 0 bpc for adjusting hdmi clockDave Airlie1-1/+1
If the bpc is set from the connector is 0, we then use it later to adjust in a special case the HDMI pixel clock, however if the bpc is 0, we end up passing a 0 pixel clock into the code. I'm not sure if this is the correct answer or if we should avoid the HDMI clock adjustment for 0 values. This fixes a divide by 0 on my Llano system with a HDMI monitor and hdmi audio enabled. Reviewed-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-12-20Merge tag 'v3.2-rc6' of /home/airlied/devel/kernel/linux-2.6 into drm-core-nextDave Airlie1-8/+33
Merge in the upstream tree to bring in the mainline fixes. Conflicts: drivers/gpu/drm/exynos/exynos_drm_fbdev.c drivers/gpu/drm/nouveau/nouveau_sgdma.c
2011-12-20drm: Replace pitch with pitches[] in drm_framebufferVille Syrjälä1-2/+2
Otherwise each driver would need to keep the information inside their own framebuffer object structure. Also add offsets[]. BOs on the other hand are driver specific, so those can be kept in driver specific structures. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-12-02drm/radeon/kms: fix scanout of 2D tiled buffers on EG/CMAlex Deucher1-2/+33
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=43191 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-11drm/radeon/kms: remove extraneous calls to radeon_pm_compute_clocks()Alex Deucher1-6/+0
It's already called via the DPMS functions. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-01drm/radeon/kms: check for DP MST mode in a few more places (v2)Alex Deucher1-2/+3
DP MST is DP multi-stream support, part of DP 1.2. v2: switch to a helper macro as suggested by Michel. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-01drm/radeon/kms: rework DP bridge checksAlex Deucher1-6/+6
Return the encoder id rather than a boolean. This is needed for differentiate between multiple DP bridge chips. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-11-01drm/radeon/kms: cleanup atombios_adjust_pll()Alex Deucher1-28/+13
The logic was messy and hard to follow. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-10-18drm/radeon/kms/DCE4.1: ss is not supported on the internal ppllsAlex Deucher1-1/+1
It's handled via external clock. It should already be protected by the external ss flag, but add an explicit check just in case. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-07-25drm/radeon: ATOM Endian fix for atombios_crtc_program_pll()Benjamin Herrenschmidt1-3/+2
v6 of the structure was programmed incorrectly: args.v6.ulCrtcPclkFreq.ulPixelClock = cpu_to_le32(clock / 10); ulPixelClock is a 24-bit bitfield. This statement would thus do a 32-bit swap of (clock / 10) and drop the top 8 bits which are ... the LSB. Not what we want. Instead use masks & shifts. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-06-17drm/radeon/kms/atom: AdjustPixelClock fixes for DP bridgesAlex Deucher1-0/+7
Need to set the external transmitter type properly in AdjustPixelClock to get the properly output. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-06-02drm/radeon/kms: viewport height has to be evenAlex Deucher1-4/+8
Otherwise, no vblank interrupts. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=37522 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-05-24drm/radeon/kms: fix typo in spread spectrum codeAlex Deucher1-1/+1
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-05-22drm/radeon/kms: the SS_Id field in the LCD table if for LVDS onlyAlex Deucher1-30/+12
For DP/eDP, always use the standard DP SS indices. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@gmail.com>
2011-05-22drm/radeon/kms: properly set the CLK_REF bit for DCE3 devicesAlex Deucher1-0/+2
If the ss clock is external, the CLK_REF bit needs to be set in the SetPixelClock parameters. This should fix DP failures in the channel equalization loop. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@gmail.com>
2011-05-20drm/radeon/kms: handle DP bridgesAlex Deucher1-2/+4
Fusion hardware often has DP to VGA/LVDS/TMDS bridges to handle non-DP encoders. Internally we treat them mostly like DP. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-05-20drm/radeon/kms: fix up DP clock programming on DCE4/5Alex Deucher1-2/+10
In DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, depending on the asic. The crtc virtual pixel clock is derived from the DP ref clock. - DCE4: PPLL or ext clock - DCE5: DCPLL or ext clock Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip PPLL/DCPLL programming and only program the DP DTO for the crtc virtual pixel clock. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-05-20drm/radeon/kms: spread spectrum fixesAlex Deucher1-16/+36
- properly mask the ss type - don't enable ss if type is external or percentage is 0 - if ss enabled and type is external, set ref_div_src to ext clock - prefer ASIC_INTERNAL_SS_ON_DP to LCD_Info SS_Id for eDP - fix ss amount calculation Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-05-20drm/radeon/kms: properly handle bpc >8 in atom command tablesAlex Deucher1-4/+34
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-04-20drm/radeon/kms: pll tweaks for r7xxAlex Deucher1-5/+1
Prefer min m to max p only on pre-r7xx asics. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=36197 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-04-09drm/radeon/kms: pll tweaks for rv6xxAlex Deucher1-0/+6
Prefer minm over maxp. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=35994 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-04-04drm/radeon/kms: pageflipping cleanup for avivo+Alex Deucher1-0/+20
Avoid touching the flip setup regs while acceleration is running. Set them at modeset rather than during pageflip. Touching these regs while acceleration is active caused hangs on pre-avivo chips. These chips do not seem to be affected, but better safe than sorry, plus it avoids repeatedly reprogramming the regs every flip. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-23drm/radeon/kms: prefer legacy pll algo for tv-outAlex Deucher1-1/+5
ntsc seems to work fine with either algo, some pal TVs seem pickier. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=30832 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-16drm/radeon/kms: fix typo in atom overscan setupAlex Deucher1-2/+2
Typo in the aspect scale setup. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-03-14Merge remote branch 'intel/drm-intel-next' of ../drm-next into drm-core-nextDave Airlie1-58/+42
* 'intel/drm-intel-next' of ../drm-next: (755 commits) drm/i915: Only wait on a pending flip if we intend to write to the buffer drm/i915/dp: Sanity check eDP existence drm/i915: Rebind the buffer if its alignment constraints changes with tiling drm/i915: Disable GPU semaphores by default drm/i915: Do not overflow the MMADDR write FIFO Revert "drm/i915: fix corruptions on i8xx due to relaxed fencing" drm/i915: Don't save/restore hardware status page address register drm/i915: don't store the reg value for HWS_PGA drm/i915: fix memory corruption with GM965 and >4GB RAM Linux 2.6.38-rc7 Revert "TPM: Long default timeout fix" drm/i915: Re-enable GPU semaphores for SandyBridge mobile drm/i915: Replace vblank PM QoS with "Interrupt-Based AGPBUSY#" Revert "drm/i915: Use PM QoS to prevent C-State starvation of gen3 GPU" drm/i915: Allow relocation deltas outside of target bo drm/i915: Silence an innocuous compiler warning for an unused variable fs/block_dev.c: fix new kernel-doc warning ACPI: Fix build for CONFIG_NET unset mm: <asm-generic/pgtable.h> must include <linux/mm_types.h> x86: Use u32 instead of long to set reset vector back to 0 ... Conflicts: drivers/gpu/drm/i915/i915_gem.c
2011-02-23drm/radeon: introduce gem_to_radeon_bo helperDaniel Vetter1-4/+4
... and switch it to container_of upcasting. v2: converted new pageflip code-paths. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-17drm/radeon/kms: add missing frac fb div flag for dce4+Alex Deucher1-1/+3
The fixed ref/post dividers are set by the AdjustPll table rather than the ss info table on dce4+. Make sure we enable the fractional feedback dividers when using a fixed post or ref divider on them as well. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=29272 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-15drm/radeon/kms: hopefully fix pll issues for real (v3)Alex Deucher1-14/+8
The problematic boards have a recommended reference divider to be used when spread spectrum is enabled on the laptop panel. Enable the use of the recommended reference divider along with the new pll algo. v2: testing options v3: When using the fixed reference divider with LVDS, prefer min m to max p and use fractional feedback dividers. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=28852 https://bugzilla.kernel.org/show_bug.cgi?id=24462 https://bugzilla.kernel.org/show_bug.cgi?id=26552 MacbookPro issues reported by Justin Mattock <justinmattock@gmail.com> Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-15drm/radeon/kms: fix a few more atombios endian issuesAlex Deucher1-1/+1
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-14drm/radeon/kms: atombios big endian fixesCédric Cano1-26/+26
agd5f: additional cleanups/fixes Signed-off-by: Cédric Cano <ccano@interfaceconcept.com> Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-14drm/radeon/kms: fix interlaced modes on dce4+Alex Deucher1-17/+5
- set scaler table clears the interleave bit, need to reset it in encoder quirks, this was already done for pre-dce4. - remove the interleave settings from set_base() functions this is now handled in the encoder quirks functions, and isn't technically part of the display base setup. - rename evergreen_do_set_base() to dce4_do_set_base() since it's used on both evergreen and NI asics. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=28182 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-02drm/radeon/kms: Enable new pll calculation for avivo+ asicsAlex Deucher1-2/+16
New algo is used for r5xx+ and legacy is used for r1xx-r4xx, rv515. I've tested on all relevant GPUs and monitors that I have access to and have found no problems. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=26562 https://bugzilla.kernel.org/show_bug.cgi?id=26552 May fix: https://bugs.freedesktop.org/show_bug.cgi?id=32556 Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-02-02drm/radeon/kms: add new pll algo for avivo asicsAlex Deucher1-2/+2
Based on the vbios code. This should hopefully fix the pll problems on a number of avivo asics once it's enabled. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-01-27drm/radeon/kms: fix r6xx+ scanout on BE systemsAlex Deucher1-0/+17
R6xx+ have per-block swappers. BE content in the framebuffer will now be swapped properly during scanout. Untested, however, the same code is reported working in the UMS ddx. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@gmail.com>
2011-01-24drm/radeon/kms: simplify atom adjust pll setupAlex Deucher1-17/+5
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@gmail.com>
2011-01-07drm/radeon/kms: DCE5 atom spread spectrum updatesAlex Deucher1-1/+25
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-06 22:23:41 +0000