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path: root/drivers/gpu/drm/nouveau
AgeCommit message (Expand)AuthorFilesLines
2010-12-21drm/nvc0: create shared channel vmBen Skeggs1-0/+16
2010-12-21drm/nvc0: initial vm implementation, use for bar1/bar3 managementBen Skeggs8-204/+266
2010-12-21drm/nvc0: import initial vm backendBen Skeggs7-7/+169
2010-12-21drm/nouveau: modify vm to accomodate dual page tables for nvc0Ben Skeggs4-75/+65
2010-12-21drm/nv50: add missing license header to nv50_fbcon.cBen Skeggs1-0/+24
2010-12-21drm/nv50: fix smatch warning in nv50_vram.cBen Skeggs1-1/+2
2010-12-21drm/nouveau: sizeof() vs ARRAY_SIZE()Dan Carpenter1-1/+1
2010-12-16drm/nv50: fix a couple of vm init issuesFrancisco Jerez1-6/+7
2010-12-08drm/nv04-nv40: Fix up PCI(E) GART DMA object bus address calculation.Francisco Jerez3-18/+10
2010-12-08drm/nouveau: kick vram functions out into an "engine"Ben Skeggs7-51/+74
2010-12-08drm/nouveau: allow gpuobj vinst to be a virtual address when necessaryBen Skeggs2-2/+24
2010-12-08drm/nv50: tidy up PCIEGART implementationBen Skeggs5-95/+79
2010-12-08drm/nv50: enable non-contig vram allocations where requestedBen Skeggs1-1/+5
2010-12-08drm/nv50: enable 4KiB pages for small vram allocationsBen Skeggs2-19/+25
2010-12-08drm/nv50: implement global channel address space on new VM codeBen Skeggs13-216/+86
2010-12-08drm/nv50: implement BAR1/BAR3 management on top of new VM codeBen Skeggs4-153/+162
2010-12-08drm/nv50: import new vm codeBen Skeggs11-22/+714
2010-12-08drm/nv50: implement custom vram mmBen Skeggs8-122/+650
2010-12-08drm/nouveau: Avoid potential race between nouveau_fence_update() and context ...Francisco Jerez1-8/+11
2010-12-08drm/nouveau: fix use of drm_mm_node in semaphore objectBen Skeggs1-3/+2
2010-12-08drm/nouveau: wrap calls to ttm_bo_validate()Ben Skeggs3-5/+20
2010-12-08drm/nouveau: no need to zero dma objects, we fill them completely anywayBen Skeggs1-5/+2
2010-12-08drm/nouveau: introduce a util function to wait on reg != valBen Skeggs4-13/+35
2010-12-08drm/nouveau: implicitly insert non-DMA objects into RAMHTBen Skeggs6-80/+43
2010-12-08drm/nouveau: make fifo.create_context() responsible for mapping control regsBen Skeggs5-21/+29
2010-12-08drm/nouveau: Spin for a bit in nouveau_fence_wait() before yielding the CPU.Francisco Jerez1-1/+2
2010-12-08drm/nouveau: Use WC memory on the AGP GART.Francisco Jerez1-2/+3
2010-12-08drm/nouveau: Synchronize with the user channel before GPU object destruction.Francisco Jerez4-28/+28
2010-12-08drm/nv04-nv10: Don't re-enable FIFO access multiple times after IRQ dispatch.Francisco Jerez2-15/+0
2010-12-08drm/nv04-nv40: Give "gpuobj->cinst" the same meaning as on nv50.Francisco Jerez3-13/+3
2010-12-03drm/nouveau: fabricate DCB encoder table for iMac G4Francisco Jerez1-64/+38
2010-12-03drm/nouveau: tidy up and extend dma object creation interfacesBen Skeggs8-160/+184
2010-12-03drm/nouveau: remove some useless GETPARAMsBen Skeggs1-16/+1
2010-12-03drm/nv84: fix minor issues in PCRYPT implementationBen Skeggs2-1/+2
2010-12-03drm/nouveau: remove dummy page use from PCI(E)GART, use PTE present insteadBen Skeggs2-37/+3
2010-12-03drm/nv50: fix 0x100c90 init for NVAFBen Skeggs1-3/+6
2010-12-03drm/nv50: allocate page for unknown PFB object in nv50_fb.cBen Skeggs2-1/+56
2010-12-03drm/nouveau: rework gpu-specific instmem interfacesBen Skeggs6-243/+270
2010-12-03drm/nouveau: simplify gpuobj suspend/resumeBen Skeggs4-73/+21
2010-12-03drm/nv50: rework PGPIO IRQ handling and hotplug detectionBen Skeggs7-104/+234
2010-12-03drm/nv04-nv40: unregister irq handler on destroyBen Skeggs1-0/+3
2010-12-03drm/nouveau: tidy+move PGRAPH ISRs to their respective *_graph.c filesBen Skeggs8-894/+809
2010-12-03drm/nouveau: move PFIFO ISR into nv04_fifo.cBen Skeggs7-208/+219
2010-12-03drm/nv04-nv40: register vblank isrBen Skeggs2-19/+18
2010-12-03drm/nouveau: move bitfield/enum helpers to nouveau_util.cBen Skeggs3-68/+63
2010-12-03drm/nv50: use register/unregister functionality for PDISPLAY ISRBen Skeggs4-18/+13
2010-12-03drm/nv50: move GPIO ISR to nv50_gpio.cBen Skeggs5-24/+40
2010-12-03drm/nv84: move PCRYPT ISR out of nouveau_irq.cBen Skeggs5-25/+98
2010-12-03drm/nouveau: allow irq handlers to be installed by engine-specific codeBen Skeggs2-1/+37
2010-12-03drm/nv50: 0x50c0 apparently works on NVA3+ too, so lets allow itBen Skeggs1-5/+4
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