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path: root/drivers/gpu/drm/nouveau/nva3_pm.c
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2012-05-24drm/nouveau/pm: some more delays for ddr3 reclockingBen Skeggs1-0/+1
These numbers from the binary driver's daemon scripts, and fix the transition to perflvl 3 on my T510. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nva3/pm: another few magic regs, and slightly better 0x004018 handlingBen Skeggs1-4/+15
Not entirely convinced 0x004018 transitions are correct yet, but, it's an improvement. The 750MHz value comes from fiddling with the binary driver + coolbits on two different DDR3 NVA8 chipsets (T510 NVS3100M, and NVS300), not a clue where this number comes from. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nva3/pm: initial attempt at handling 111100/111104Ben Skeggs1-0/+21
Probably not quite right, but this is enough now to make NVS300 reclock between all 3 of its perflvls correctly. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nva3/pm: make pll->pll mode workBen Skeggs1-6/+21
This probably wants a cleanup, but I'm holding off until I know for sure how the rest of the things that need doing fit together. Tested on NVS300 by hacking up perflvl 1 to require PLL mode, and switching between perflvl 3 and 1. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nva3/pm: attempt to bash a few 0x100200 bits correctlyBen Skeggs1-20/+46
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nva3/pm: begin to restructure memory clock changes + another magicBen Skeggs1-8/+40
The binary driver appears to do various bits and pieces of the memory clock frequency change at different times, depending on the particular transition that's occuring. I've attempted to replicate this here for div->pll, pll->div and div->div transitions. With some additional (patches upcoming) magic regs being bashed, this allows me to correctly transition between all 3 perflvls on NVS300. pll->pll transitions will *not* work correctly at the moment, pending me tricking the binary driver into doing one and seeing how to correctly handle it. This patch also handles (hopefully) 0x1110e0, which appears to need changing depending on whether in PLL or divider mode.. Maybe. We'll see. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nva3/pm: more random unknown PFB regsBen Skeggs1-1/+23
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nva3/pm: initial attempt at more magic PFB regsBen Skeggs1-1/+24
The reg calculation may get moved elsewhere at some point, but lets figure out what exactly we need to do first. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nva3/pm: hook up to ram reclocking helperBen Skeggs1-12/+110
This gets us a start on memory timings. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2012-05-24drm/nva3/pm: introduce more paranoiaBen Skeggs1-5/+10
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-12-21drm/nouveau/pm: make clocks_set return an error code clocks_set can fail.Martin Peres1-1/+5
Reporting an error is better than silently refusing to reclock. V2: Use the same logic on nv40 Signed-off-by: Martin Peres <martin.peres@labri.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20drm/nva3/pm: fixup for NVAF specialBen Skeggs1-1/+7
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20drm/nva3/pm: use crystal freq where appropriateBen Skeggs1-3/+4
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20drm/nva3/pm: pll disabled if bit 0 of ctrl not setBen Skeggs1-19/+23
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20drm/nvc0/pm: more complete parsing of clock domainsBen Skeggs1-0/+2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20drm/nva3/pm: idle graphics engine before changing clocksBen Skeggs1-0/+40
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20drm/nva3/pm: tidy and add some comments here and thereBen Skeggs1-47/+78
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20drm/nva3/pm: parse/reclock vdec/41a0 clocksBen Skeggs1-0/+20
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20drm/nva3/pm: rewrite clock_set, and switch to new interfacesBen Skeggs1-136/+141
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-09-20drm/nva3/pm: rewrite clock readback functions, far more correct nowBen Skeggs1-33/+62
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nva3/clk: better pll calculation when no fractional fb div availableBen Skeggs1-2/+2
The core/mem/shader clocks don't support the fractional feedback divider, causing our calculated clocks to be off by quite a lot in some cases. To solve this we will switch to a search-based algorithm when fN is NULL. For my NVA8 at PL3, this actually generates identical cooefficients to the binary driver. Hopefully that's a good sign, and that does not break VPLL calculation for someone.. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nva3/pm: allow use of divisor 16Ben Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nva3/pm: initial pass at set_clock() hookBen Skeggs1-21/+94
I still discourage anyone from actually doing this yet. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nva3: somewhat improve clock reportingBen Skeggs1-10/+46
Definitely not 100% correct, but, for the configurations I've seen used it'll read back the correct clocks now. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2010-10-05drm/nva3: split pm backend out from nv50Ben Skeggs1-0/+95
This will end up quite different, it makes sense for it to be completely separate. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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