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2018-03-19drm/msm: rename mdp->dispRob Clark1-1968/+0
Since new display controller is called "dpu" instead of "mdp". Lets make the name of the toplevel directory for the display controllers a bit more generic. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Sean Paul <seanpaul@chromium.org>
2017-06-16drm/msm: update generated headersRob Clark1-3/+11
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-02-06drm/msm/mdp5: Update generated headersArchit Taneja1-23/+25
Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-11-28drm/msm: update generated headersRob Clark1-3/+11
Pull in a5xx registers. Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-07-16drm/msm/mdp5: Use updated MDP5 register namesArchit Taneja1-110/+93
Since MDSS registers were stuffed within the the MDP5 register space, we had an __offset_MDP() macro to identify the offset between the start of MDSS and MDP5 address spaces. This offset macro expected a MDP index argument, which didn't make much sense since we don't have multiple MDPs. The offset is no longer needed now that we have devices for the 2 different register address spaces. Also, remove the "REG_MDP5_MDP_" prefix to "REG_MDP5_". Update the generated headers in mdp5.xml.h We generally update headers as a separate patch, but we need to do these together to prevent breaking build. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-03-03drm/msm: update generated headersRob Clark1-2/+3
Pull in additional regs needed for a430, etc. Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-10-22drm/msm: update generated headersRob Clark1-4/+82
Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-08-15drm/msm: update generated headersRob Clark1-61/+119
Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-06-11drm/msm: update generated headersRob Clark1-15/+383
Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Update headers (add CTL flush bits)Stephane Viau1-2/+10
Some upcoming targets have more bits to set in CTL_FLUSH registers. Example: msm8x16 needs to set TIMING1 bit so that some of the INTF1's interface registers get flushed. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Update headers (remove enum mdp5_client_id)Stephane Viau1-34/+7
This patch contains the generated header file of the following change "drm/msm/mdp5: Get SMP client list from mdp5_cfg". Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Update headers (introduce MDP5 domain)Stephane Viau1-85/+118
This change contains the generated header file for the following change "drm/msm/mdp5: Separate MDP5 domain from MDSS domain". Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Update generated mdp5 header file with DSI supportHai Li1-0/+105
This change adds the registers in mdp5 ping pong blocks and split display control registers. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Update generated header filesStephane Viau1-35/+33
Prepare for pipeline operation mode configuration, in particular for DSI and WB modes. Signed-off-by: Stephane Viau <sviau@codeaurora.org> [Throw in a #define temporarily to keep things bisectable -Rob] Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-03-04drm/msm: update generated headers (add 6th lm.base entry)Stephane Viau1-11/+4
Some target have up to 6 layer mixers (LM). Let the header file access the last LM's base address. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-02-01drm/msm: update generated headersRob Clark1-16/+229
Resync from rnndb database, to pull in register defines for: * eDP * HDMI/HDCP * mdp4/mdp5 YUV support * mdp5 hw cursor support Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-11-16drm/msm: update generated headersRob Clark1-5/+5
Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-08-04drm/msm/mdp5: add support for MDP5 v1.3Stephane Viau1-161/+264
MDP5 has several functional blocks (ie: VIG/RGB pipes, LMs, ...). From one revision to another, these blocks' base addresses might change due to the number of instances present in the MDP5 hw. A way of dealing with these offset changes is to introduce dynamic offsets 'per block'. This change adds support for the new revision of MDP5: v1.3. The idea is to define one hw config per MDP version and select either one of them at runtime, after reading the MDP5 version. Once the MDP version is known, 'per block' dynamic offsets are initialized through a global pointer, which is then used for read/write register access. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-08-04drm/msm: update generated headersRob Clark1-3/+3
Signed-off-by: Rob Clark <robdclark@gmail.com>
2014-01-09drm/msm: resync generated headersRob Clark1-0/+1036
resync to latest envytools db, add mdp5 registers Signed-off-by: Rob Clark <robdclark@gmail.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-07 19:08:15 +0000