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2019-11-08Merge tag 'mediatek-drm-next-5.5-2' of ↵Dave Airlie6-42/+205
https://github.com/ckhu-mediatek/linux.git-tags into drm-next Mediatek DRM next for Linux 5.5 - 2 Signed-off-by: Dave Airlie <airlied@redhat.com> From: CK Hu <ck.hu@mediatek.com> Link: https://patchwork.freedesktop.org/patch/msgid/1573093419.13645.5.camel@mtksdaap41
2019-11-06drm/mediatek: Support 180 degree rotationSean Paul1-2/+2
Now that we support both reflections, we can expose 180 degree rotation and rely on the simplify routine to convert that into REFLECT_X | REFLECT_Y Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-11-06drm/mediatek: Support reflect-x plane rotationSean Paul1-1/+9
Add support for REFLECT_X rotations. Cc: Fritz Koenig <frkoenig@chromium.org> Cc: Daniele Castagna <dcastagna@chromium.org> Cc: Miguel Casas <mcasas@chromium.org> Cc: Mark Yacoub <markyacoub@google.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-11-06drm/mediatek: Support reflect-y plane rotationSean Paul1-0/+42
Expose the rotation property and handle REFLECT_Y rotations. Cc: Fritz Koenig <frkoenig@chromium.org> Cc: Daniele Castagna <dcastagna@chromium.org> Cc: Miguel Casas <mcasas@chromium.org> Cc: Mark Yacoub <markyacoub@google.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-11-06drm/mediatek: Plumb supported rotation values from components to plane initSean Paul4-3/+27
This patch adds the ability for components to expose supported rotations which will be exposed to userspace via a plane rotation property. No functional changes in this patch. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-11-06drm/mediatek: Add plumbing for layer_check hookSean Paul4-0/+30
This allows components to implement a .layer_check callback for their layers which is called during atomic_check. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-11-06drm/mediatek: Add helper to get component for a planeSean Paul1-22/+34
Instead of hard-coding which components have planes, add a helper function to walk the components and map a plane index to a component layer. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-11-06drm/mediatek: Refactor plane initSean Paul1-18/+59
Add a couple of functions which enumerate the number of planes for a component and initialize the planes for a component. No functional changes in this patch, but it will allow us to selectively support rotation if the component supports it. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-11-06drm/mediatek: Add RGB[A] variants to published plane formatsSean Paul1-0/+6
These formats are handled in the rdma code, but for some reason they're not published as supported formats for the planes. So add them to the list. Cc: Nicolas Boichat <drinkcat@chromium.org> Cc: Daniele Castagna <dcastagna@chromium.org> Cc: Miguel Casas <mcasas@chromium.org> Tested-by: Miguel Casas <mcasas@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-24drm/mediatek: remove cast to pointers passed to kfreeWambui Karuga1-2/+2
Remove unnecessary casts to pointer types passed to kfree. Issue detected by coccinelle: @@ type t1; expression *e; @@ -kfree((t1 *)e); +kfree(e); Signed-off-by: Wambui Karuga <wambui.karugax@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20191023111107.9972-1-wambui.karugax@gmail.com
2019-10-22Merge tag 'mediatek-drm-next-5.5' of ↵Dave Airlie12-421/+955
https://github.com/ckhu-mediatek/linux.git-tags into drm-next Mediatek DRM next for Linux 5.5 This include mipi_tx, dsi, and partial crtc for MT8183 SoC. Signed-off-by: Dave Airlie <airlied@redhat.com> From: CK Hu <ck.hu@mediatek.com> Link: https://patchwork.freedesktop.org/patch/msgid/1571103548.4416.6.camel@mtksdaap41
2019-10-09drm/mediatek: add no_clk into ddp private dataCK Hu1-6/+9
Mutex has no clock in some SoC, so add no_clk in private data and get clock according to no_clk. Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-09drm/mediatek: add mutex sof register offset into ddp private dataYongqiang Niu1-3/+10
mutex sof register offset will be private data of ddp Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-09drm/mediatek: add mutex sof into ddp private dataYongqiang Niu1-8/+35
mutex sof will be ddp private data Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-09drm/mediatek: add mutex mod register offset into ddp private dataYongqiang Niu1-8/+16
mutex mod register offset will be private data of ddp. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-09drm/mediatek: add mutex mod into ddp private dataYongqiang Niu1-11/+30
except mutex mod, mutex mod reg,mutex sof reg, and mutex sof id will be ddp private data Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-09drm/mediatek: add ovl0/ovl_2l0 usecaseYongqiang Niu1-3/+34
This patch add ovl0/ovl_2l0 usecase in ovl->ovl_2l0 direct link usecase: 1. the crtc support layer number will 4+2 2. ovl_2l0 background color input select ovl0 when crtc init and disable it when crtc finish 3. config ovl_2l0 layer, if crtc config layer number is bigger than ovl0 support layers(max is 4) Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-09drm/mediatek: distinguish ovl and ovl_2l by layer_nrYongqiang Niu1-3/+6
distinguish ovl and ovl_2l by layer_nr when get comp id Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-09drm/mediatek: add background color input select function for ovl/ovl_2lYongqiang Niu1-0/+22
This patch add background color input select function for ovl/ovl_2l ovl include 4 DRAM layer and 1 background color layer ovl_2l include 4 DRAM layer and 1 background color layer DRAM layer frame buffer data from render hardware, GPU for example. backgournd color layer is embed in ovl/ovl_2l, we can only set it color, but not support DRAM frame buffer. for ovl0->ovl0_2l direct link usecase, we need set ovl0_2l background color intput select from ovl0 if render send DRAM buffer layer number <=4, all these layer read by ovl. layer0 is at the bottom of all layers. layer3 is at the top of all layers. if render send DRAM buffer layer numbfer >=4 && <=6 ovl0 read layer0~3 ovl0_2l read layer4~5 layer5 is at the top ot all these layers. the decision of how to setting ovl0/ovl0_2l read these layer data is controlled in mtk crtc, which will be another patch Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-09drm/mediatek: add function to background color input select for ovl/ovl_2l ↵Yongqiang Niu1-0/+14
direct link This patch add function to background color input select for ovl/ovl_2l direct link for ovl/ovl_2l direct link usecase, we need set background color input select for these hardware. This is preparation patch for ovl/ovl_2l usecase. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-09drm/medaitek: add layer_nr for ovl private dataYongqiang Niu1-1/+6
This patch add layer_nr for ovl private data ovl_2l almost same with with ovl hardware, except the layer number for ovl_2l is 2 and ovl is 4. this patch is a preparation for ovl-2l and ovl share the same driver. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-09drm/mediatek: add gmc_bits for ovl private dataYongqiang Niu1-2/+21
This patch add gmc_bits for ovl private data GMC register was set RDMA ultra and pre-ultra threshold. 10bit GMC register define is different with other SOC, gmc_thrshd_l not used. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-09drm/mediatek: add component OVL_2L1Yongqiang Niu2-0/+2
This patch add component OVL_2L1 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-09drm/mediatek: add component OVL_2L0Yongqiang Niu3-0/+5
This patch add component OVL_2L0 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-09drm/mediatek: add component DITHERYongqiang Niu2-0/+34
This patch add component DITHER Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-09drm/mediatek: add ddp component CCORRYongqiang Niu2-0/+34
This patch add ddp component CCORR Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-07drm/mediatek: add dphy reset after setting lanes numberJitao Shi1-0/+9
Add dphy reset after setting lanes number to avoid dphy fifo effor. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-07drm/mediatek: adjust dsi and mipi_tx probe sequenceJitao Shi1-1/+1
mtk_mipi_tx is the phy of mtk_dsi. mtk_dsi get the phy(mtk_mipi_tx) in probe(). So, mtk_mipi_tx init should be ahead of mtk_dsi. Or mtk_dsi will defer to wait mtk_mipi_tx probe done. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-07drm/mediatek: change the dsi phytiming calculate methodJitao Shi1-37/+81
Change the method of frame rate calc which can get more accurate frame rate. data rate = pixel_clock * bit_per_pixel / lanes Adjust hfp_wc to adapt the additional phy_data if MIPI_DSI_MODE_VIDEO_BURST hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12 - 6; else hfp_wc = hfp * bpp - data_phy_cycles * lanes - 12; Note: //(2: 1 for sync, 1 for phy idle) data_phy_cycles = T_hs_exit + T_lpx + T_hs_prepare + T_hs_zero + 2; bpp: bit per pixel Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Tested-by: Ryan Case <ryandcase@chromium.org> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-07drm/mediatek: add mt8183 dsi driver supportJitao Shi1-0/+8
Add mt8183 dsi driver data. Enable size control and reg commit control. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-07drm/mediatek: add frame size controlJitao Shi1-0/+6
Our new DSI chip has frame size control. So add the driver data to control for different chips. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-07drm/mediatek: add dsi reg commit disable controlJitao Shi1-0/+10
New DSI IP has shadow register and working reg. The register values are writen to shadow register. And then trigger with commit reg, the register values will be moved working register. This function is default on. But this driver doesn't use this function. So add the disable control. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-07drm/mediatek: replace writeb() with mtk_dsi_mask()Jitao Shi1-1/+3
The writeb() is unavailable in mt8173. Because the mt8173 dsi module doesn't support 8bit mode access. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-07drm/mediatek: fixes CMDQ reg address of mt8173 is different with mt2701Jitao Shi1-5/+22
Config the different CMDQ reg address in driver data. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-07drm/mediatek: move mipi_dsi_host_register to probeJitao Shi1-22/+31
DSI panel driver need attach function which is include in mipi_dsi_host_ops. If mipi_dsi_host_register is not in probe, dsi panel will probe more delay. So move the mipi_dsi_host_register to probe from bind. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-07drm/mediatek: add mipi_tx driver for mt8183Jitao Shi4-0/+153
This patch add mt8183 mipi_tx driver. And also support other chips that use the same binding and driver. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-07drm/mediatek: separate mipi_tx to different fileJitao Shi4-315/+358
Different IC has different mipi_tx setting of dsi. This patch separates the mipi_tx hardware relate part for mt8173. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-10-03Merge drm/drm-next into drm-misc-nextMaxime Ripard2-3/+53
We haven't done any backmerge for a while due to the merge window, and it starts to become an issue for komeda. Let's bring 5.4-rc1 in. Signed-off-by: Maxime Ripard <mripard@kernel.org>
2019-09-19Merge tag 'drm-next-2019-09-18' of git://anongit.freedesktop.org/drm/drmLinus Torvalds13-83/+62
Pull drm updates from Dave Airlie: "This is the main pull request for 5.4-rc1 merge window. I don't think there is anything outstanding so next week should just be fixes, but we'll see if I missed anything. I landed some fixes earlier in the week but got delayed writing summary and sending it out, due to a mix of sick kid and jetlag! There are some fixes pending, but I'd rather get the main merge out of the way instead of delaying it longer. It's also pretty large in commit count and new amd header file size. The largest thing is four new amdgpu products (navi12/14, arcturus and renoir APU support). Otherwise it's pretty much lots of work across the board, i915 has started landing tigerlake support, lots of icelake fixes and lots of locking reworking for future gpu support, lots of header file rework (drmP.h is nearly gone), some old legacy hacks (DRM_WAIT_ON) have been put into the places they are needed. uapi: - content protection type property for HDCP core: - rework include dependencies - lots of drmP.h removals - link rate calculation robustness fix - make fb helper map only when required - add connector->DDC adapter link - DRM_WAIT_ON removed - drop DRM_AUTH usage from drivers dma-buf: - reservation object fence helper dma-fence: - shrink dma_fence struct - merge signal functions - store timestamps in dma_fence - selftests ttm: - embed drm_get_object struct into ttm_buffer_object - release_notify callback bridges: - sii902x - audio graph card support - tc358767 - aux data handling rework - ti-snd64dsi86 - debugfs support, DSI mode flags support panels: - Support for GiantPlus GPM940B0, Sharp LQ070Y3DG3B, Ortustech COM37H3M, Novatek NT39016, Sharp LS020B1DD01D, Raydium RM67191, Boe Himax8279d, Sharp LD-D5116Z01B - TI nspire, NEC NL8048HL11, LG Philips LB035Q02, Sharp LS037V7DW01, Sony ACX565AKM, Toppoly TD028TTEC1 Toppoly TD043MTEA1 i915: - Initial tigerlake platform support - Locking simplification work, general all over refactoring. - Selftests - HDCP debug info improvements - DSI properties - Icelake display PLL fixes, colorspace fixes, bandwidth fixes, DSI suspend/resume - GuC fixes - Perf fixes - ElkhartLake enablement - DP MST fixes - GVT - command parser enhancements amdgpu: - add wipe memory on release flag for buffer creation - Navi12/14 support (may be marked experimental) - Arcturus support - Renoir APU support - mclk DPM for Navi - DC display fixes - Raven scatter/gather support - RAS support for GFX - Navi12 + Arcturus power features - GPU reset for Picasso - smu11 i2c controller support amdkfd: - navi12/14 support - Arcturus support radeon: - kexec fix nouveau: - improved display color management - detect lack of GPU power cables vmwgfx: - evicition priority support - remove unused security feature msm: - msm8998 display support - better async commit support for cursor updates etnaviv: - per-process address space support - performance counter fixes - softpin support mcde: - DCS transfers fix exynos: - drmP.h cleanup lima: - reduce logging kirin: - misc clenaups komeda: - dual-link support - DT memory regions hisilicon: - misc fixes imx: - IPUv3 image converter fixes - 32-bit RGB V4L2 pixel format support ingenic: - more support for panel related cases mgag200: - cursor support fix panfrost: - export GPU features register to userspace - gpu heap allocations - per-fd address space support pl111: - CLD pads wiring support removed from DT rockchip: - rework to use DRM PSR helpers - fix bug in VOP_WIN_GET macro - DSI DT binding rework sun4i: - improve support for color encoding and range - DDC enabled GPIO tinydrm: - rework SPI support - improve MIPI-DBI support - moved to drm/tiny vkms: - rework CRC tracking dw-hdmi: - get_eld and i2s improvements gm12u320: - misc fixes meson: - global code cleanup - vpu feature detect omap: - alpha/pixel blend mode properties rcar-du: - misc fixes" * tag 'drm-next-2019-09-18' of git://anongit.freedesktop.org/drm/drm: (2112 commits) drm/nouveau/bar/gm20b: Avoid BAR1 teardown during init drm/nouveau: Fix ordering between TTM and GEM release drm/nouveau/prime: Extend DMA reservation object lock drm/nouveau: Fix fallout from reservation object rework drm/nouveau/kms/nv50-: Don't create MSTMs for eDP connectors drm/i915: Use NOEVICT for first pass on attemping to pin a GGTT mmap drm/i915: to make vgpu ppgtt notificaiton as atomic operation drm/i915: Flush the existing fence before GGTT read/write drm/i915: Hold irq-off for the entire fake lock period drm/i915/gvt: update RING_START reg of vGPU when the context is submitted to i915 drm/i915/gvt: update vgpu workload head pointer correctly drm/mcde: Fix DSI transfers drm/msm: Use the correct dma_sync calls harder drm/msm: remove unlikely() from WARN_ON() conditions drm/msm/dsi: Fix return value check for clk_get_parent drm/msm: add atomic traces drm/msm/dpu: async commit support drm/msm: async commit support drm/msm: split power control from prepare/complete_commit drm/msm: add kms->flush_commit() ...
2019-08-28drm: Stop including drm_bridge.h from drm_crtc.hBoris Brezillon3-0/+3
We are about to add a drm_bridge_state that inherits from drm_private_state which is defined in drm_atomic.h. Problem is, drm_atomic.h includes drm_crtc.h which in turn includes drm_bridge.h, leading to "drm_private_state has incomplete type" error. Let's force all users of the drm_bridge API to explicitly include drm_bridge.h. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Sam Ravnborg <sam@ravnborg.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190826152649.13820-2-boris.brezillon@collabora.com
2019-08-24drm/mediatek: include dma-mapping headerDave Airlie1-0/+1
Although it builds fine here in my arm cross compile, it seems either via some other patches in -next or some Kconfig combination, this fails to build for everyone. Include linux/dma-mapping.h should fix it. Signed-off-by: Dave Airlie <airlied@redhat.com>
2019-08-19drm/mediatek: mtk_drm_drv.c: Add of_node_put() before gotoNishka Dasgupta1-1/+4
Each iteration of for_each_child_of_node puts the previous node, but in the case of a goto from the middle of the loop, there is no put, thus causing a memory leak. Hence add an of_node_put before the goto in two places. Issue found with Coccinelle. Fixes: 119f5173628a (drm/mediatek: Add DRM Driver for Mediatek SoC MT8173) Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-08-15drm/mediatek: set DMA max segment sizeAlexandre Courbot2-2/+35
This driver requires imported PRIME buffers to appear contiguously in its IO address space. Make sure this is the case by setting the maximum DMA segment size to a more suitable value than the default 64KB. Signed-off-by: Alexandre Courbot <acourbot@chromium.org> Reviewed-by: Tomasz Figa <tfiga@chromium.org> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-08-15drm/mediatek: use correct device to import PRIME buffersAlexandre Courbot1-1/+13
PRIME buffers should be imported using the DMA device. To this end, use a custom import function that mimics drm_gem_prime_import_dev(), but passes the correct device. Fixes: 119f5173628aa ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.") Signed-off-by: Alexandre Courbot <acourbot@chromium.org> Signed-off-by: CK Hu <ck.hu@mediatek.com>
2019-08-13dma-buf: rename reservation_object to dma_resvChristian König1-1/+1
Be more consistent with the naming of the other DMA-buf objects. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/323401/
2019-07-19drm/mediatek: direct include of drm.h in mtk_drm_gem.cSam Ravnborg1-0/+1
Do not rely on including drm.h from drm_file.h, as the include in drm_file.h will be dropped. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Sean Paul <sean@poorly.run> Acked-by: CK Hu <ck.hu@mediatek.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Link: https://patchwork.freedesktop.org/patch/msgid/20190718161507.2047-11-sam@ravnborg.org
2019-07-17drm/mediatek: drop use of drmP.hSam Ravnborg12-39/+56
Drop use of the deprecated drmP.h header file. While touching the include files divide them up in blocks in the typical order: \#include <linux/*> \#include <video/*> \#include <drm/*> \#include "" And sort the includes in the blocks Add the necessary includes to fix build after removal of drmP.h Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Acked-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Link: https://patchwork.freedesktop.org/patch/msgid/20190716064220.18157-20-sam@ravnborg.org
2019-06-25drm/mediatek: Use drm_atomic_helper_wait_for_fencesDaniel Vetter4-40/+3
If we use the gem fb helper as the prepare_fb hook, plus the drm_prime.c import helpers now automatically setting obj->resv, we can use the shared helpers to wait for fences instead of rolling our own. Note that this relies on mtk setting drm_fb->obj, which is already done in mtk_drm_framebuffer_init(). Aside: Probably can use the default commit_tail with this again, but I didn't check for that. Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Cc: CK Hu <ck.hu@mediatek.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Link: https://patchwork.freedesktop.org/patch/msgid/20190614203615.12639-45-daniel.vetter@ffwll.ch
2019-06-21drm/mtk: Drop drm_gem_prime_export/importDaniel Vetter1-2/+0
They're the default. Aside: Would be really nice to switch the others over to drm_gem_object_funcs. Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Cc: CK Hu <ck.hu@mediatek.com> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Link: https://patchwork.freedesktop.org/patch/msgid/20190614203615.12639-20-daniel.vetter@ffwll.ch
2019-06-21drm/prime: Actually remove DRIVER_PRIME everywhereDaniel Vetter1-2/+1
Split out to make the functional changes stick out more. All places where DRIVER_PRIME was used have been removed in previous patches already. v2: amdgpu gained DRIVER_SYNCOBJ_TIMELINE. v3: amdgpu lost DRIVER_SYNCOBJ_TIMELINE. v4: Don't add a space in i915_drv.c (Sam) v5: Add note that previous patches removed all the DRIVER_PRIME users already (Emil). v6: Fixupe ingenic (new driver) while applying. Cc: Sam Ravnborg <sam@ravnborg.org> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Cc: amd-gfx@lists.freedesktop.org Cc: etnaviv@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org Cc: intel-gfx@lists.freedesktop.org Cc: lima@lists.freedesktop.org Cc: linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-arm-msm@vger.kernel.org Cc: linux-aspeed@lists.ozlabs.org Cc: linux-renesas-soc@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com Cc: linux-tegra@vger.kernel.org Cc: nouveau@lists.freedesktop.org Cc: NXP Linux Team <linux-imx@nxp.com> Cc: spice-devel@lists.freedesktop.org Cc: virtualization@lists.linux-foundation.org Cc: VMware Graphics <linux-graphics-maintainer@vmware.com> Cc: xen-devel@lists.xenproject.org Link: https://patchwork.freedesktop.org/patch/msgid/20190617153924.414-1-daniel.vetter@ffwll.ch
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