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drivers
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gpu
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drm
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i915
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intel_cdclk.c
Age
Commit message (
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Author
Files
Lines
2017-07-03
drm/i915: reintroduce VLV/CHV PFI programming power domain workaround
Gabriel Krisman Bertazi
1
-0
/
+20
2017-06-12
drm/i915/cnl: Allow dynamic cdclk changes on CNL
Rodrigo Vivi
1
-4
/
+56
2017-06-12
drm/i915/cnl: Implement CNL display init/unit sequence
Ville Syrjälä
1
-1
/
+107
2017-06-12
drm/i915/cnl: Implement .set_cdclk() for CNL
Ville Syrjälä
1
-0
/
+106
2017-06-12
drm/i915/cnl: Implement .get_display_clock_speed() for CNL
Ville Syrjälä
1
-1
/
+55
2017-06-02
drm/i915/cnp: Get/set proper Raw clock frequency on CNP.
Rodrigo Vivi
1
-1
/
+28
2017-05-05
drm/i915: Fix rawclk readout for g4x
Ville Syrjälä
1
-4
/
+2
2017-04-06
drm/i915/glk: limit pixel clock to 99% of cdclk workaround
Madhav Chauhan
1
-3
/
+13
2017-03-22
drm/i915: Implement cdclk restrictions based on Azalia BCLK
Pandiyan, Dhinakaran
1
-0
/
+12
2017-03-22
drm/i915/glk: Apply cdclk workaround for DP audio
Pandiyan, Dhinakaran
1
-6
/
+11
2017-03-13
drm/i915: Use new atomic iterator macros in cdclk
Maarten Lankhorst
1
-1
/
+1
2017-03-07
drm/i915: remove potentially confusing IS_G4X checks
Paulo Zanoni
1
-2
/
+2
2017-02-08
drm/i915: Replace the .modeset_commit_cdclk() hook with a more direct .set_cd...
Ville Syrjälä
1
-46
/
+33
2017-02-08
drm/i915: Nuke the VLV/CHV PFI programming power domain workaround
Ville Syrjälä
1
-14
/
+0
2017-02-08
drm/i915: Move PFI credit reprogramming into vlv/chv_set_cdclk()
Ville Syrjälä
1
-1
/
+4
2017-02-08
drm/i915: Pass the cdclk state to the set_cdclk() functions
Ville Syrjälä
1
-30
/
+48
2017-02-08
drm/i915: Pass dev_priv to remainder of the cdclk functions
Ville Syrjälä
1
-15
/
+10
2017-02-08
drm/i915: Track full cdclk state for the logical and actual cdclk frequencies
Ville Syrjälä
1
-45
/
+78
2017-02-08
drm/i915: Start moving the cdclk stuff into a distinct state structure
Ville Syrjälä
1
-156
/
+226
2017-02-08
drm/i915: Pass computed vco to bxt_set_cdclk()
Ville Syrjälä
1
-14
/
+19
2017-02-08
drm/i915: Move most cdclk/rawclk related code to intel_cdclk.c
Ville Syrjälä
1
-0
/
+1794