Age | Commit message (Expand) | Author | Files | Lines |
2015-01-28 | drm/i915/skl: Enabling PSR on Skylake | Sonika Jindal | 1 | -0/+5 |
2015-01-27 | drm/i915/skl: Gen9 coarse power gating | Zhe Wang | 1 | -0/+3 |
2015-01-27 | drm/i915: New offset for reading frequencies on CHV. | Deepak S | 1 | -0/+9 |
2015-01-27 | drm/i915/chv: Populate total EU count on Cherryview | Deepak S | 1 | -0/+11 |
2015-01-13 | drm/i915: Improve HiZ throughput on Cherryview. | Kenneth Graunke | 1 | -0/+3 |
2015-01-12 | Merge tag 'topic/i915-hda-componentized-2015-01-12' into drm-intel-next-queued | Daniel Vetter | 1 | -3/+18 |
2015-01-06 | drm/i915: Make sample_c messages go faster on Haswell. | Kenneth Graunke | 1 | -0/+1 |
2014-12-16 | drm/i915: Disable PSMI sleep messages on all rings around context switches | Chris Wilson | 1 | -0/+2 |
2014-12-16 | drm/i915: Invalidate media caches on gen7 | Chris Wilson | 1 | -0/+1 |
2014-12-16 | drm/i915: Add GPGPU_THREADS_DISPATCHED to the register whitelist | Jordan Justen | 1 | -11/+12 |
2014-12-11 | drm/i915: save/restore GMBUS freq across suspend/resume on gen4 | Jesse Barnes | 1 | -0/+1 |
2014-12-10 | drm/i915: Engage the DP scramble reset for pipe C on CHV | Ville Syrjälä | 1 | -1/+2 |
2014-12-10 | drm/i915: Add MI_SET_APPID cmd to cmd parser tables | Michael H. Nguyen | 1 | -0/+3 |
2014-12-10 | drm/i915/bdw: Fix the write setting up the WIZ hashing mode | Damien Lespiau | 1 | -3/+14 |
2014-12-05 | drm/i915: Pixel Clock changes for DSI dual link | Gaurav K Singh | 1 | -0/+4 |
2014-12-05 | drm/i915: Add support for port enable/disable for dual link configuration | Gaurav K Singh | 1 | -0/+1 |
2014-12-05 | drm/i915: s/MI_STORE_DWORD_IMM_GEN8/MI_STORE_DWORD_IMM_GEN4/ | Ville Syrjälä | 1 | -2/+3 |
2014-12-03 | drm/i915/dsi: clean up MIPI DSI pipe vs. port usage | Jani Nikula | 1 | -150/+153 |
2014-12-03 | drm/i915: Add PSR registers for PSR VLV/CHV. | Rodrigo Vivi | 1 | -0/+36 |
2014-12-03 | drm/i915: Implement GPU reset for 915/945 | Ville Syrjälä | 1 | -1/+1 |
2014-12-03 | drm/i915: Fix gen4 GPU reset | Ville Syrjälä | 1 | -0/+1 |
2014-11-20 | drm/i915: Pin tiled objects for L-shaped configs | Daniel Vetter | 1 | -0/+2 |
2014-11-20 | drm/i915: Use efficient frequency for HSW/BDW | Tom O'Rourke | 1 | -0/+1 |
2014-11-17 | drm/i915: Drop the HSW special case from __gen6_gt_wait_for_thread_c0() | Ville Syrjälä | 1 | -1/+0 |
2014-11-17 | drm/i915: Add a name for the Punit GPLLENABLE bit | Ville Syrjälä | 1 | -0/+1 |
2014-11-14 | drm/i915: Clear PCODE_DATA1 on SNB+ | Damien Lespiau | 1 | -1/+1 |
2014-11-14 | drm/i915/skl: AUX irqs have moved | Jesse Barnes | 1 | -0/+3 |
2014-11-14 | drm/i915/skl: fetch, enable/disable pfit as needed v2 | Jesse Barnes | 1 | -0/+12 |
2014-11-14 | drm/i915/skl: Implement queue_flip | Damien Lespiau | 1 | -0/+10 |
2014-11-14 | drm/i915/skl: Determine enabled PLL and its linkrate/pixel clock | Satheeshakrishna M | 1 | -0/+5 |
2014-11-14 | drm/i915/skl: Register definitions for SKL Clocks | Satheeshakrishna M | 1 | -0/+72 |
2014-11-14 | drm/i915: Add the predicate source registers to the register whitelist | Neil Roberts | 1 | -0/+2 |
2014-11-14 | drm/i915/chv: Add new workarounds for chv | Arun Siluvery | 1 | -0/+1 |
2014-11-10 | Merge remote-tracking branch 'airlied/drm-next' into HEAD | Daniel Vetter | 1 | -1/+1 |
2014-11-07 | drm/i915: make pipe/port based audio valid accessors easier to use | Jani Nikula | 1 | -14/+6 |
2014-11-07 | drm/i915/skl: Gen9 Forcewake | Zhe Wang | 1 | -0/+6 |
2014-11-07 | drm/i915/skl: Program the DDB allocation | Damien Lespiau | 1 | -0/+16 |
2014-11-07 | drm/i915/skl: Register definitions and macros for SKL Watermark regs | Pradeep Bhat | 1 | -0/+35 |
2014-11-07 | drm/i915/skl: Read the Memory Latency Values for WM computation | Pradeep Bhat | 1 | -0/+7 |
2014-11-07 | drm/i915: clean up and clarify audio related register defines | Jani Nikula | 1 | -82/+83 |
2014-11-07 | Merge tag 'topic/core-stuff-2014-11-05' of git://anongit.freedesktop.org/drm-... | Dave Airlie | 1 | -1/+1 |
2014-11-04 | drm/i915: Add support for CHV pipe B sprite CSC | Ville Syrjälä | 1 | -0/+33 |
2014-11-04 | drm/i915: Initialize new chv primary plane and pipe blender registers | Ville Syrjälä | 1 | -1/+24 |
2014-10-24 | drm/i915: Add rotation support for cursor plane (v5) | Ville Syrjälä | 1 | -0/+1 |
2014-10-24 | drm/i915/chv: Use 16 and 32 for low and high drain latency precision. | Rodrigo Vivi | 1 | -6/+7 |
2014-10-24 | drm/i915: Fix chv PCS DW11 register defines | Ville Syrjälä | 1 | -2/+2 |
2014-10-24 | drm/i915/skl: Add 180 degree HW rotation support | Sonika Jindal | 1 | -0/+3 |
2014-10-21 | Merge branch 'drm-intel-next-fixes' into drm-intel-next | Daniel Vetter | 1 | -4/+3 |
2014-10-21 | gpu:drm: Fix typo in Documentation/DocBook/drm.xml | Masanari Iida | 1 | -1/+1 |
2014-10-03 | drm/i915: Clear TX FIFO reset master override bits on chv | Ville Syrjälä | 1 | -0/+12 |