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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2019-02-06drm/i915: Just use icl+ definition for PLANE_WM blocks fieldVille Syrjälä1-2/+1
2019-02-06drm/i915: Bump skl+ wm blocks to 11 bitsVille Syrjälä1-1/+1
2019-02-05drm/i915: W/A for underruns with WM1+ disabled on iclVille Syrjälä1-0/+1
2019-02-01drm/i915/icl: restore WaEnableFloatBlendOptimizationTalha Nassar1-0/+3
2019-01-30drm/i915: Force background color to black for gen9+ (v2)Matt Roper1-0/+6
2019-01-29drm/i915/icl: use tc_port in MG_PLL macrosLucas De Marchi1-26/+26
2019-01-25drm/i915/tv: Generate better pipe timings for TV encoderVille Syrjälä1-0/+1
2019-01-22drm/i915: Add PSR2 selective update status registers and bits definitionsJosé Roberto de Souza1-0/+9
2019-01-18drm/i915/dp: remove PANEL_POWER_OFF macro and its useJani Nikula1-1/+0
2019-01-17drm/i915: small isolated c99 types to kernel types switchJani Nikula1-2/+2
2019-01-15drm/i915/cnl: Fix CNL macros for Voltage Swing programmingAditya Swarup1-7/+7
2019-01-02drm/i915: always use INTEL_INFO() to access device infoJani Nikula1-6/+6
2019-01-02drm/i915/reg: abstract display_mmio_offset accessJani Nikula1-93/+95
2018-12-18drm/i915/icl: combo port vswing programming changes per BSPECClint Taylor1-0/+4
2018-12-13drm/i915/icl: Mind the SFC units when resetting VD or VEBox enginesOscar Mateo1-0/+18
2018-12-03drm/i915/icl: Define Panel power ctrl registerMadhav Chauhan1-0/+11
2018-12-03drm/i915/icl: Define missing bitfield for shortplug regMadhav Chauhan1-0/+1
2018-11-29i915/dp/fec: Configure the Forward Error Correction bits.Anusha Srivatsa1-0/+2
2018-11-29drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPsManasi Navare1-0/+1
2018-11-21drm/i915: Make CHICKEN_TRANS reg not depend on enum valueImre Deak1-3/+4
2018-11-21drm/i915: Make EDP PSR flags not depend on enum valuesImre Deak1-3/+7
2018-11-19Revert "drm/i915/perf: add a parameter to control the size of OA buffer"Joonas Lahtinen1-2/+0
2018-11-14drm/i915: Deduplicate register definition for GAMW_ECO_DEV_RW_IAMika Kuoppala1-3/+1
2018-11-13drm/i915: rename CNP_RAWCLK_FRAC to CNP_RAWCLK_DENPaulo Zanoni1-2/+1
2018-11-09drm/i915: Polish the skl+ plane keyval/msk/max register setupVille Syrjälä1-1/+1
2018-11-06drm/i915/icl: Define Plane Input CSC Coefficient RegistersUma Shankar1-0/+50
2018-11-02drm/i915/fia: FIA registers offset implementation.Anusha Srivatsa1-4/+6
2018-11-02drm/i915: also group device info array helper macros with othersJani Nikula1-12/+14
2018-11-02drm/i915: reorder and reindent the register choosing helper wrappersJani Nikula1-14/+17
2018-11-02drm/i915: define _MMIO_PLANE() in terms of _PLANE() not _MMIO_PIPE()Jani Nikula1-1/+1
2018-11-02drm/i915: remove palette_offsets from device info in favor of _PICK()Jani Nikula1-9/+7
2018-11-01drm/i915/icl: Fix DSS_CTL register namesAnusha Srivatsa1-11/+11
2018-11-01drm/i915/icl: WaAllowUMDToModifySamplerModeOscar Mateo1-0/+2
2018-11-01drm/i915/icl: Add WaEnable32PlaneModeRadhakrishna Sripada1-0/+1
2018-11-01drm/i915/icl: Add DSS_CTL RegistersAnusha Srivatsa1-0/+33
2018-11-01drm/i915/icl: Add DSI packet payload/header registersMadhav Chauhan1-0/+22
2018-10-31drm/i915/icl: Fix the macros for DFLEXDPMLE register bitsManasi Navare1-2/+6
2018-10-31drm/i915/dsc: Add slice_row_per_frame in DSC PPS programmingAnusha Srivatsa1-0/+1
2018-10-31drm/i915/icl: Define DSI timeout registersMadhav Chauhan1-0/+43
2018-10-29drm/i915: Move VIDEO_DIP_CTL definitions to their right place.Dhinakaran Pandiyan1-10/+9
2018-10-29drm/i915: Fix VIDEO_DIP_CTL bit shiftsDhinakaran Pandiyan1-6/+6
2018-10-29drm/i915: Define Intel HDCP2.2 registersRamalingam C1-0/+32
2018-10-24drm/i915/gen11: Program the Y and UV plane for planar mode correctly, v3.Maarten Lankhorst1-0/+1
2018-10-24drm/i915/gen11: Program the chroma upsampler for HDR planes.Maarten Lankhorst1-0/+22
2018-10-24drm/i915/gen11: Program the scalers correctly for planar formats, v3.Maarten Lankhorst1-1/+3
2018-10-23drm/i915/perf: add a parameter to control the size of OA bufferLionel Landwerlin1-0/+2
2018-10-22drm/i915/icl: Define DSI panel programming registersMadhav Chauhan1-0/+38
2018-10-22drm/i915/icl: Define TRANS_CONF register for DSIMadhav Chauhan1-0/+8
2018-10-22drm/i915/icl: Define DSI transcoder timing registersMadhav Chauhan1-0/+14
2018-10-22drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registersMadhav Chauhan1-0/+17
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