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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2019-09-23drm/i915/color: Extract icl_read_luts()Swati Sharma1-0/+6
2019-09-21drm/i915/tgl: s/ss/eu fuse reading supportDaniele Ceraolo Spurio1-0/+2
2019-09-20drm/i915: Add PIPECONF YCbCr 4:4:4 programming for ILK-IVBVille Syrjälä1-0/+4
2019-09-20drm/i915: Set up ILK/SNB csc unit properly for YCbCr outputVille Syrjälä1-5/+5
2019-09-20drm/i915: Add PIPECONF YCbCr 4:4:4 programming for HSWVille Syrjälä1-0/+1
2019-09-20drm/i915: Simplify intel_get_crtc_ycbcr_config()Ville Syrjälä1-2/+2
2019-09-20drm/i915: Fix HSW+ DP MSA YCbCr colorspace indicationVille Syrjälä1-1/+2
2019-09-20Revert "drm/i915/tgl: Implement Wa_1406941453"Chris Wilson1-3/+0
2019-09-19drm/i915/tgl: Implement Wa_1406941453Michel Thierry1-0/+3
2019-09-19drm/i915/tgl: Implement Wa_1409142259Radhakrishna Sripada1-0/+1
2019-09-10drm/i915/display: Extract chv_read_luts()Swati Sharma1-0/+3
2019-09-10drm/i915/display: Extract i965_read_luts()Swati Sharma1-0/+4
2019-09-04drm/i915/tgl: move DP_TP_* to transcoderLucas De Marchi1-0/+4
2019-09-04drm/i915/tgl: Access the right register when handling PSR interruptionsJosé Roberto de Souza1-1/+9
2019-09-04drm/i915/psr: Only handle interruptions of the transcoder in useJosé Roberto de Souza1-7/+6
2019-09-04drm/i915/display: Extract glk_read_luts()Swati Sharma1-0/+3
2019-09-04drm/i915/display: Extract ilk_read_luts()Swati Sharma1-0/+3
2019-09-04drm/i915/display: Extract i9xx_read_luts()Swati Sharma1-0/+3
2019-08-30drm/i915: Allow /2 CD2X divider on gen11+Matt Roper1-0/+3
2019-08-30drm/i915: parameterize SDE hotplug registersLucas De Marchi1-20/+15
2019-08-30drm/i915: parameterize south hpd macrosLucas De Marchi1-24/+12
2019-08-30drm/i915/hdcp: Enable HDCP 1.4 and 2.2 on Gen12+Ramalingam C1-9/+115
2019-08-23drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gatingMichel Thierry1-0/+4
2019-08-22drm/i915/psr: Make PSR registers relative to transcodersJosé Roberto de Souza1-18/+39
2019-08-20drm/i915/tgl: Updated Private PAT programmingMichel Thierry1-0/+1
2019-08-16drm/i915: Move gmbus definitions out of i915_reg.hDaniele Ceraolo Spurio1-21/+1
2019-08-16drm/i915: Move engine IDs out of i915_reg.hDaniele Ceraolo Spurio1-24/+3
2019-08-16drm/i915: Move i915_power_well_id out of i915_reg.hDaniele Ceraolo Spurio1-21/+0
2019-08-13drm/i915: Add _TRANS2()José Roberto de Souza1-3/+4
2019-08-13drm/i915/tgl: Fix missing parentheses on TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORTJosé Roberto de Souza1-1/+1
2019-08-08drm/i915/tgl: Fix the read of the DDI that transcoder is attached toJosé Roberto de Souza1-0/+2
2019-08-08drm/i915/tgl/dsi: Enable blanking packets during BLLP for video modeVandita Kulkarni1-0/+1
2019-08-01drm/i915/tgl: Add and use new DC5 and DC6 residency counter registersJosé Roberto de Souza1-0/+2
2019-07-31drm/i915/tgl: Tigerlake only has global MOCS registersMichel Thierry1-0/+2
2019-07-31drm/i915/tgl: Move fault registers to their new offsetLucas De Marchi1-0/+3
2019-07-30drm/i915/tgl: handle DP aux interruptsLucas De Marchi1-0/+3
2019-07-30drm/i915/tgl: Update north display hotplug detection to TGL connectionsJosé Roberto de Souza1-2/+10
2019-07-30drm/i915/tgl: Add hpd interrupt handlingLucas De Marchi1-1/+27
2019-07-26drm/i915/tgl: update ddi/tc clock_off bitsMahesh Kumar1-2/+3
2019-07-26drm/i915/tgl: select correct bit for port selectMahesh Kumar1-3/+8
2019-07-19drm/i915/icl: Add Wa_1409178092Tvrtko Ursulin1-0/+3
2019-07-13drm/i915/guc: unify guc irq handlingDaniele Ceraolo Spurio1-10/+0
2019-07-12drm/i915: Add modular FIAAnusha Srivatsa1-4/+9
2019-07-12drm/i915: Add test for invalid flag bits in whitelist entriesJohn Harrison1-3/+9
2019-07-11drm/i915/tgl: Update DPLL clock reference registerJosé Roberto de Souza1-0/+1
2019-07-11drm/i915/tgl: Add DPLL registersLucas De Marchi1-0/+17
2019-07-11drm/i915/tgl: Add gmbus gpio pin to port mappingMahesh Kumar1-1/+3
2019-07-11drm/i915/tgl: apply Display WA #1178 to fix type C donglesLucas De Marchi1-1/+3
2019-07-11drm/i915/tgl: Add power well to support 4th pipeMika Kahola1-0/+1
2019-07-11drm/i915/tgl: Add power well supportImre Deak1-1/+19
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