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path: root/drivers/gpu/drm/i915/gvt/render.c
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2017-12-08drm/i915/gvt: Rename file render.{c, h} to mmio_context.{c, h}Changbin Du1-403/+0
Rename the files to reflect their real role - to switch the mmio context of each vGPU engine. v2: update Makefile. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-12-08drm/i915/gvt: Remove MMIO barrier in MMIO switchChangbin Du1-12/+0
After engine mmio switched, software still need write workload submission registers. So we can remove the MMIO barriar in MMIO switch. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-12-08drm/i915/gvt: Select appropriate mmio list at initialization timeChangbin Du1-33/+27
Select appropriate mmio list at initialization time, so we don't need to do duplicated work at where requires the mmio list. V2: - Add a termination mark of mmio list. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-12-08drm/i915/gvt: Refine the ring mmio list definitionChangbin Du1-90/+104
To improve the readability, let's remove the hard code for each mmio definition. The raw offset remained as a comment, which give us an offset based view. This refine is to make it convenient for new platform enabling. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-11-16drm/i915/gvt: Reduce rcs mocs switch latencyChangbin Du1-1/+1
Use I915_WRITE_FW instead of I915_WRITE to reduce overhead. The overall mmio switch latency lowers from ~600us to ~180us. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-11-16drm/i915/gvt: Move tlb_handle_pending into intel_vgpu_submissionZhi Wang1-1/+2
Move tlb_handle_pending into intel_vgpu_submssion since it belongs to a part of vGPU submission stuffs Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
2017-11-16drm/i915/gvt: Introduce intel_vgpu_submissionZhi Wang1-4/+5
Introduce intel_vgpu_submission to hold all members related to submission in struct intel_vgpu before. Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
2017-09-22drm/i915: Rename global i915 to i915_modparamsMichal Wajdeczko1-1/+1
Our global struct with params is named exactly the same way as new preferred name for the drm_i915_private function parameter. To avoid such name reuse lets use different name for the global. v5: pure rename v6: fix Credits-to: Coccinelle @@ identifier n; @@ ( - i915.n + i915_modparams.n ) Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Ville Syrjala <ville.syrjala@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Acked-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170919193846.38060-1-michal.wajdeczko@intel.com
2017-08-10drm/i915/gvt: Optimize ring siwtch 2x faster again by light weight mmio ↵Changbin Du1-13/+26
access wrapper The I915_READ/WRITE is not only a mmio read/write, it also contains debug checking and Forcewake domain lookup. This is too heavy for GVT ring switch case which access batch of mmio registers on ring switch. We can handle Forcewake manually and use the raw i915_read/write instead. The benefit from this is 2x faster mmio switch performance. Before After cycles ~550000 ~250000 v2: Use existing I915_READ_FW/I915_WRITE_FW macro. (zhenyu) Signed-off-by: Changbin Du <changbin.du@intel.com> Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-08-10drm/i915/gvt: Optimize ring siwtch 2x faster by removing unnecessary ↵Changbin Du1-6/+13
POSTING_READ There are lots of POSTING_READ alongside each mmio write Op. While actually this is not necessary. It just bring too much latency since PCIe read Op is very slow which is of non-posted transaction. For PCIe device, the mem transaction for strong ordering rules are: o PCIe mmio write sequence is FIFO. Posted request cannot pass previous posted request. o PCIe mmio read will not go ahead of previous write. Intel graphics doesn't support RO, so we can apply above rules. In our case, we only need one POSTING_READ at last. This can remove half of mmio read Op and then the average ring switch performance is nearly doubled. Before After cycles ~970000 ~550000 Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-06-16Merge tag 'gvt-next-2017-06-08' of https://github.com/01org/gvt-linux into ↵Jani Nikula1-8/+40
drm-intel-next-queued gvt-next-2017-06-08 First gvt-next pull for 4.13: - optimization for per-VM mmio save/restore (Changbin) - optimization for mmio hash table (Changbin) - scheduler optimization with event (Ping) - vGPU reset refinement (Fred) - other misc refactor and cleanups, etc. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170608093547.bjgs436e3iokrzdm@zhen-hp.sh.intel.com
2017-06-08drm/i915/gvt: Change flood gvt dmesg into traceXiong Zhang1-6/+7
Currently gvt dmesg is so heavy at drm.debug=0x2 that guest and host almost couldn't run on xengt. This patch transfer these repeated messages into trace, so dmesg is light at drm.debug=0x2, and user could get the target message through trace event and trace filter. Suggested-by: Zhi Wang <zhi.a.wang@intel.com> Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-06-08drm/i915/gvt: implement per-vm mmio switching optimizationChangbin Du1-2/+33
Commit ab9da627906a ("drm/i915: make context status notifier head be per engine") gives us a chance to inspect every single request. Then we can eliminate unnecessary mmio switching for same vGPU. We only need mmio switching for different VMs (including host). This patch introduced a new general API intel_gvt_switch_mmio() to replace the old intel_gvt_load/restore_render_mmio(). This function can be further optimized for vGPU to vGPU switching. To support individual ring switch, we track the owner who occupy each ring. When another VM or host request a ring we do the mmio context switching. Otherwise no need to switch the ring. This optimization is very useful if only one guest has plenty of workloads and the host is mostly idle. The best case is no mmio switching will happen. v2: o fix missing ring switch issue. (chuanxiao) o support individual ring switch. Signed-off-by: Changbin Du <changbin.du@intel.com> Reviewed-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-05-15Merge tag 'gvt-fixes-2017-05-11' of https://github.com/01org/gvt-linux into ↵Jani Nikula1-0/+3
drm-intel-fixes gvt-fixes-2017-05-11 - vGPU scheduler performance regression fix (Ping) - bypass in-context mmio restore (Chuanxiao) - one typo fix (Colin) Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170511054736.swpcmnzdoqi75cnl@zhen-hp.sh.intel.com
2017-05-08drm/i915/gvt: not to restore in-context mmioChuanxiao Dong1-0/+3
Needn't to restore the in-context MMIO when SCHEDULE_OUT. Sometimes with restoring the in-context MMIO, some GPU hang can be observed. So remove the in-context MMIO restore Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-04-26Merge tag 'gvt-next-fixes-2017-04-20' of https://github.com/01org/gvt-linux ↵Jani Nikula1-8/+2
into drm-intel-next-fixes gvt-next-fixes-2017-04-20 - some code optimization from Changbin - debug message cleanup after QoS merge - misc fixes for display mmio init, reset vgpu warning, etc. Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2017-04-12drm/i915/gvt: remove redundant platform check for mocs load/restoreChangbin Du1-6/+0
The platform check is done outside, no need check again. Platform doesn't include mocs should not invoke this two functions. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-04-12drm/i915/gvt: Align render mmio list to cachelineChangbin Du1-2/+2
Make the global mmio list be cacheline aligned to improve performance. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-04-11Backmerge tag 'v4.11-rc6' into drm-nextDave Airlie1-1/+1
Linux 4.11-rc6 drm-misc needs 4.11-rc5, may as well fix conflicts with rc6.
2017-03-29drm/i915/gvt: Add KBL dispatch logic in each function.Xu Han1-5/+6
Extend function dispatch logic to support KBL platform. Signed-off-by: Xu Han <xu.han@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-03-29drm/i915/gvt: Update save/restore list to compatible KBL platform.Xu Han1-0/+12
Add some KBL specially registers to save/restore list. Signed-off-by: Xu Han <xu.han@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-03-21drm/i915/gvt: fix wrong offset when loading RCS mocsChuanxiao Dong1-1/+1
Fix the wrong offset of the RCS specific mocs Fixes: 178657139307 ("drm/i915/gvt: vGPU context switch") Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-03-17drm/i915/gvt: replace the gvt_err with gvt_vgpu_errTina Zhang1-1/+1
gvt_err should be used only for the very few critical error message during host i915 drvier initialization. This patch 1. removes the redundant gvt_err; 2. creates a new gvt_vgpu_err to show errors caused by vgpu; 3. replaces the most gvt_err with gvt_vgpu_err; 4. leaves very few gvt_err for dumping gvt error during host gvt initialization. v2. change name to gvt_vgpu_err and add vgpu id to the message. (Kevin) add gpu id to gvt_vgpu_err. (Zhi) v3. remove gpu id from gvt_vgpu_err caller. (Zhi) v4. add vgpu check to the gvt_vgpu_err macro. (Zhiyuan) v5. add comments for v3 and v4. v6. split the big patch into two, with this patch only for checking gvt_vgpu_err. (Zhenyu) v7. rebase to staging branch v8. rebase to fix branch Signed-off-by: Tina Zhang <tina.zhang@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-02-23drm/i915/gvt: add more registers to context save/restore listZhao Yan1-0/+16
the value of those registers should be applied to hardware on context restoring Signed-off-by: Zhao Yan <yan.y.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2017-02-14drm/i915/gvt: optimize the inhibit context mmio loadChuanxiao Dong1-0/+17
For the inhibit ctx, load all mmio in render mmio list into HW by MMIO write for ctx initialization. For the none-inhibit ctx, only load the render mmio which is not in_context into HW by MMIO write. Skip the MMIO write for in_context mmio as context image will load it. Signed-off-by: Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2016-11-07drm/i915/gvt: correct the emulation in TLB control handlerPing Gao1-0/+2
Need a explicit write_vreg in TLB MMIO write handler, beside that TLB vreg should update correspondingly following HW status to do correct emulation. Signed-off-by: Ping Gao <ping.a.gao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2016-10-24drm/i915/gvt: Fix broken mocs offsetZhenyu Wang1-0/+2
Fix missed mocs offset reg setting for save/restore function. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2016-10-24drm/i915/gvt: Implement WaForceWakeRenderDuringMmioTLBInvalidateArkadiusz Hiler1-2/+17
When invalidating RCS TLB the device can enter RC6 state interrupting the process, therefore the need for render forcewake for the whole procedure. This WA is needed for all production SKL SKUs. v2: reworked putting and getting forcewake with help of Mika Kuoppala v3: use I915_READ_FW and I915_WRITE_FW as we are handling forcewake on in the code path References: HSD#2136899, HSD#1404391274 Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2016-10-20drm/i915/gvt: clean up intel_gvt.h as interface for i915 coreZhenyu Wang1-0/+1
i915 core should only call functions and structures exposed through intel_gvt.h. Remove internal gvt.h and i915_pvinfo.h. Change for internal intel_gvt structure as private handler which not requires to expose gvt internal structure for i915 core. v2: Fix per Chris's comment - carefully handle dev_priv->gvt assignment - add necessary bracket for macro helper - forward declartion struct intel_gvt - keep free operation within same file handling alloc v3: fix use after free and remove intel_gvt.initialized v4: change to_gvt() to an inline Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2016-10-14drm/i915/gvt: vGPU context switchZhi Wang1-0/+290
As different VM may configure different render MMIOs when executing workload, to schedule workloads between different VM, the render MMIOs have to be switched. Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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