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path: root/drivers/gpu/drm/i915/gt
AgeCommit message (Expand)AuthorFilesLines
2020-05-25drm/i915/gt: Remove errant assertion in __intel_context_do_pinChris Wilson1-2/+0
2020-05-14drm/i915/gt: Transfer old virtual breadcrumbs to irq_workerChris Wilson4-34/+57
2020-05-14drm/i915: Show per-engine default property values in sysfsChris Wilson3-1/+97
2020-05-14drm/i915: Drop no-semaphore boostingChris Wilson2-9/+1
2020-05-13drm/i915: Mark the addition of the initial-breadcrumb in the requestChris Wilson1-1/+4
2020-05-13drm/i915: Remove duplicate inline specifier on write_pteNathan Chancellor1-1/+1
2020-05-13drm/i915/gt: Suspend tasklets before resume sanitizationChris Wilson1-4/+4
2020-05-13drm/i915/gt: Reset execlists registers before HWSPChris Wilson1-7/+14
2020-05-12drm/i915/ehl: Restrict w/a 1607087056 for EHL/JSLSwathi Dhanavanthri1-4/+7
2020-05-11drm/i915/gt: Restore Cherryview back to full-ppgttChris Wilson1-0/+54
2020-05-11drm/i915/gt: Force pte cacheline to main memoryMika Kuoppala1-2/+13
2020-05-11drm/i915/selftests: Always flush before unpining after writingChris Wilson2-0/+4
2020-05-11drm/i915: Emit await(batch) before MI_BB_STARTChris Wilson1-7/+9
2020-05-11drm/i915: Make intel_timeline_init staticMika Kuoppala2-9/+4
2020-05-11drm/i915/gt: Mark up the racy read of execlists->context_tagChris Wilson1-1/+1
2020-05-09drm/i915: Replace zero-length array with flexible-arrayGustavo A. R. Silva1-1/+1
2020-05-08drm/i915/gt: Improve precision on defer_request assertChris Wilson1-1/+2
2020-05-07drm/i915/gen12: Add aux table invalidate for all enginesMika Kuoppala1-5/+81
2020-05-07drm/i915: Remove wait priority boostingChris Wilson2-4/+2
2020-05-07drm/i915: Mark concurrent submissions with a weak-dependencyChris Wilson1-0/+3
2020-05-07drm/i915/gen12: Invalidate aux table entries forciblyMika Kuoppala1-1/+15
2020-05-07drm/i915/gen12: Flush L3Mika Kuoppala1-0/+2
2020-05-07drm/i915/gen12: Fix HDC pipeline flushMika Kuoppala3-21/+44
2020-05-07Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"Mika Kuoppala2-2/+0
2020-05-05drm/i915/gt: Stop holding onto the pinned_default_stateChris Wilson5-46/+47
2020-05-05drm/i915/execlists: Record the active CCID from before resetChris Wilson2-1/+8
2020-05-05drm/i915/gt: Small tidy of gen8+ breadcrumb emissionChris Wilson1-19/+15
2020-05-04drm/i915/selftests: Repeat the rps clock frequency measurementChris Wilson1-14/+40
2020-05-04drm/i915: Remove cnl pre-prod workaroundsVille Syrjälä2-24/+1
2020-05-04drm/i915/gem: Implement legacy MI_STORE_DATA_IMMChris Wilson1-31/+2
2020-05-03drm/i915/gt: Sanitize RPS interrupts upon resumeChris Wilson3-1/+7
2020-05-01drm/i915/gt: Make timeslicing an explicit engine propertyChris Wilson3-14/+18
2020-04-30drm/i915/gt: Move the batch buffer pool from the engine to the gtChris Wilson10-94/+136
2020-04-30drm/i915/gt: Restore aggressive post-boost downclockingChris Wilson1-16/+4
2020-04-30drm/i915/gt: Apply the aggressive downclocking to parkingChris Wilson1-4/+9
2020-04-30drm/i915/gt: Switch to manual evaluation of RPSChris Wilson4-16/+147
2020-04-30drm/i915/gt: Track use of RPS interrupts in flagsChris Wilson4-6/+29
2020-04-30drm/i915/gt: Move rps.enabled/active to flagsChris Wilson5-32/+76
2020-04-30drm/i915/gt: Always enable busy-stats for execlistsChris Wilson4-128/+24
2020-04-29drm/i915/gt: Keep a no-frills swappable copy of the default context stateChris Wilson11-97/+289
2020-04-29drm/i915/selftests: fix error handling in __live_lrc_indirect_ctx_bb()Dan Carpenter1-12/+18
2020-04-29drm/i915/gt: Avoid uninitialized use of rpcurupei in frequency_showNathan Chancellor1-1/+1
2020-04-28drm/i915/execlists: Verify we don't submit two identical CCIDsChris Wilson1-9/+28
2020-04-28drm/i915/execlists: Track inflight CCIDChris Wilson2-9/+23
2020-04-28drm/i915/execlists: Avoid reusing the same logical CCIDChris Wilson5-36/+40
2020-04-28drm/i915/selftests: Tweak the tolerance for clock ticks to 12.5%Chris Wilson1-4/+4
2020-04-28drm/i915/gt: fix spelling mistake "evalution" -> "evaluation"Colin Ian King1-1/+1
2020-04-27drm/i915/gt: Fix up clock frequencyChris Wilson4-6/+147
2020-04-27drm/i915/gt: Sanitize GT firstChris Wilson2-1/+5
2020-04-27drm/i915/gt: Check cacheline is valid before acquiringChris Wilson1-0/+2
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