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2017-09-12drm/amdgpu: fixed raven psp cmd prepare and submitEvan Quan1-7/+9
- fw_size in psp_v10_0_prep_cmd_buf is wrongly set as 0 - fixed the wrong calculation of psp_write_ptr_reg in psp_v10_0_cmd_submit Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-12drm/amdgpu: move MMU notifier related defines to amdgpu_mn.hChristian König2-24/+53
Just some cleanup. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-12drm/amdgpu: move amdgpu_ttm_tt_* declarations into amdgpu_ttm.hChristian König2-15/+16
Just some cleanup. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-12drm/amdgpu: keep the MMU lock until the update ends v4Christian König2-6/+57
This is quite controversial because it adds another lock which is held during page table updates, but I don't see much other option. v2: allow multiple updates to be in flight at the same time v3: simplify the patch, take the read side only once v4: correctly fix rebase conflict Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-12drm/amdgpu: rework amdgpu_cs_find_mappingChristian König4-32/+30
Use the VM instead of the BO list to find the BO for a virtual address. This fixes UVD/VCE in physical mode with VM local BOs. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-12drm/amdgpu: move amdgpu_cs_sysvm_access_required into find_mappingChristian König4-63/+36
When we need to find the mapping we need sysvm access anyway. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-12drm/amdgpu: stop reserving the BO in the MMU callback v3Christian König3-15/+56
Instead take the callback lock during the final parts of CS. This should solve the last remaining locking order problems with BO reservations. v2: rebase, make dummy functions static inline v3: add one more missing inline and comments Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-12drm/amdgpu: use a rw_semaphore for MMU notifiersChristian König1-13/+13
Allow at least some parallel processing. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-12drm/amdgpu: move userptr BOs to CPU domain during CS v2Christian König4-12/+27
Instead of moving them in the MMU notifier move them during CS. v2: still mark pages as accessed/dirty Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-12drm/amdgpu: stop using BO status for user pagesChristian König3-4/+22
Instead use a counter to figure out if we need to set new pages or not. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-12drm/amdgpu: move taking mmap_sem into get_user_pages v2Christian König3-16/+8
This didn't helped as intended, just simplify the code. v2: unlock mmap_sem in the error path as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-12drm/amdgpu: Account for shadow PTs in mapping update IB size.Bas Nieuwenhuizen1-2/+4
When amdgpu_vm_frag_ptes calls amdgpu_vm_update_ptes and the pt has a shadow PT we mirror all the write to the shadow PT too, which results in twice the commands. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-12drm/amdgpu: revert "fix deadlock of reservation between cs and gpu reset v2"Christian König1-4/+0
This reverts commit 10e709cb296c98424c03408d23e3addeddcd4088. The patch doesn't work at all: 1. The CS can still be blocked because of amdgpu_ctx_add_fence(). 2. The order of submission isn't correct any more. 3. We could end up using freed up memory because we now drop the ctx reference to early. This needs to be fixed cleanly by doing the context handling after the BO handling, but this is a larger task just avoid the obvious crashes for now. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Monk Liu monk.liu@amd.com Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-12drm/amd/powerplay: Fix psm_set_user_performance_state()Tom St Denis3-7/+7
We now pass a pointer to a pointer which seems to be what they meant in the first place. The previous version was modifying a pointer passed by value. Fixes bug that was introduced by commit 332798d40c2e91:drm/amd/powerplay: delete eventmgr layer in poweprlay Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-By: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-12drm/amdgpu: fix userptr put_page handlingChristian König3-5/+16
Move calling put_page into the unpopulate callback. Otherwise we mess up the pages reference count when it is unbound multiple times. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-12drm/amdgpu: fix wait_any_fenceMonk Liu1-0/+1
first is incorrect if hit NULL/signaled fence Signed-off-by: Monk Liu <monk.liu@amd.com> Reviewed-by: Chunming Zhou <David1.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-12drm/amd/powerplay: set uvd/vce/nb/mclk level as UMD P-state requiredRex Zhu1-3/+9
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-12drm/amd/powerplay: add UMD P-state in powerplay.Rex Zhu5-132/+66
This feature is for UMD to run benchmark in a power state that is as steady as possible. kmd need to fix the power state as stable as possible. now, kmd support four level: profile_standard,peak,min_sclk,min_mclk move common related code to amd_powerplay.c Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-12drm/amd/powerplay: delete eventmgr related files.Rex Zhu16-2405/+0
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-12drm/amd/powerplay: delete eventmgr layer in poweprlayRex Zhu13-282/+475
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-01drm/amd/powerplay: fix sclk setting for profile mode for CZ/STAlex Deucher1-46/+1
Need to select dpm0 to avoid clock fluctuations. Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-01drm/amdgpu: Use correct path to trace includeThierry Reding2-3/+1
The header comment in include/trace/define_trace.h specifies that the TRACE_INCLUDE_PATH needs to be relative to the define_trace.h header rather than the trace file including it. Most instances get that wrong and work around it by adding the $(src) directory to the include path. While this works, it is preferable to refer to the correct path to the trace file in the first place and avoid any workaround. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-01drm/amd/amdgpu: Cleanup gmc_v9_0_suspend()Tom St Denis1-3/+1
Even though fini returns 0 always it could theoretically fail in the future. Might as well return it instead of 0. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-01drm/amd/amdgpu: Tidy up gmc_v9_0_hw_init()Tom St Denis1-8/+2
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-01drm/amd/amdgpu: Tidy up gmc_v9_0_gart_enable()Tom St Denis1-5/+1
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-01drm/amd/amdgpu: Simplify gmc_v9_0_vm_fault_interrupt_state()Tom St Denis1-34/+17
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-01drm/amd/amdgpu: Support full range of GFX ring namesTom St Denis1-1/+4
Right now there's only one but the rest of the code is being setup to support more so might as well fix this up too. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-01drm/amdgpu: fix placement flags in amdgpu_ttm_bindChristian König1-1/+1
Otherwise we lose the NO_EVICT flag and can try to evict pinned BOs. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-01drm/amdgpu: fix moved list handling in the VMChristian König1-3/+6
Only move BOs to the moved/relocated list when they aren't already on a list. This prevents accidential removal from the evicted list. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-01drm/amdgpu: declare the new firmware files needed by polaris asicsEvan Quan1-0/+15
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Flora Cui <Flora.Cui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-01drm/amdgpu: handle all fragment sizes v4Roger He1-29/+26
This can improve performance for some cases. v2 (chk): handle all sizes, simplify the patch quite a bit v3 (chk): adjust dw estimation as well v4 (chk): use single loop, make end mask 64bit Signed-off-by: Roger He <Hongbo.He@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Tested-by: Roger He <Hongbo.He@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-31drm/amd/amdgpu: Simplify gfx_v9_0_wait_for_idle()Tom St Denis1-6/+1
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-31drm/amd/amdgpu: Fix indentation in gfx_v9_0_mqd_init()Tom St Denis1-2/+2
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-31drm/amd/amdgpu: Tidy up gfx_v9_0_rlc_stop()Tom St Denis1-6/+1
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-31drm/amd/amdgpu: Tidy up gfx_v9_0_enable_gfx_dynamic_mg_power_gating()Tom St Denis1-4/+3
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-31drm/amd/amdgpu: Tidy up gfx_v9_0_enable_gfx_static_mg_power_gating()Tom St Denis1-4/+3
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-31drm/amd/amdgpu: Tidy up gfx_v9_0_enable_gfx_pipeline_powergating()Tom St Denis1-4/+3
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-31drm/amd/amdgpu: Tidy up gfx_v9_0_enable_gfx_cg_power_gating()Tom St Denis1-4/+3
Make it consistent in style with the other CG/PG enable functions... Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-31drm/amd/amdgpu: Tidy up gfx_v9_0_enable_cp_power_gating()Tom St Denis1-10/+5
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-31drm/amd/amdgpu: Tidy up gfx_v9_0_enable_sck_slow_down_on_power_down()Tom St Denis1-10/+5
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-31drm/amd/amdgpu: Tidy up gfx_v9_0_enable_sck_slow_down_on_power_up()Tom St Denis1-10/+5
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-31drm/amd/amdgpu: Tidy up gfx_v9_0_enable_save_restore_machine()Tom St Denis1-5/+1
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-31drm/amd/amdgpu: Tidy up gfx_v9_0_ngg_en()Tom St Denis1-17/+9
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-31drm/amd/amdgpu: Tidy up register list formatting.Tom St Denis1-32/+64
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-31drm/amdgpu: bump version for support of local BOsChristian König1-1/+2
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-31drm/amdgpu: add IOCTL interface for per VM BOs v3Christian König4-22/+53
Add the IOCTL interface so that applications can allocate per VM BOs. Still WIP since not all corner cases are tested yet, but this reduces average CS overhead for 10K BOs from 21ms down to 48us. v2: add some extra checks, remove the WIP tag v3: rename new flag to AMDGPU_GEM_CREATE_VM_ALWAYS_VALID Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-31drm/amdgpu: add support for per VM BOs v2Christian König3-26/+60
Per VM BOs are handled like VM PDs and PTs. They are always valid and don't need to be specified in the BO lists. v2: validate PDs/PTs first Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-31drm/amdgpu: restrict userptr even moreChristian König1-0/+6
Don't allow them to be GEM imported into another process. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-31drm/amdgpu: fix new PD update code for Vega10 v2Christian König1-2/+2
We need to refer to the parent instead of the root BO for multi level page tables on Vega10. Also don't set the PDE_PTE bit. v2: Don't set the PDE_PTE bit either. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-and-Tested-by: Roger He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-31drm/amdgpu: move hw generation check into amdgpu_doorbell_init v2Christian König1-5/+12
This way we can safely call it on SI as well. v2: fix type in commit message Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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