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path: root/drivers/gpu/drm/amd/pm
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2021-07-13drm/amd/pm: Add waiting for response of mode-reset message for yellow carpAaron Liu1-7/+3
Remove mdelay process and use smu_cmn_send_smc_msg_with_param to send mode-reset message to SMC. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-13drm/amd/pm: Fix BACO state setting for Beige_GobyChengming Gui1-0/+1
Correct BACO state setting for Beige_Goby Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-13drm/amd/pm: drop smu_v13_0_1.c|h files for yellow carpXiaomeng Hou6-377/+57
Since there's nothing special in smu implementation for yellow carp, it's better to reuse the common smu_v13_0 interfaces and drop the specific smu_v13_0_1.c|h files. v2: remove the duplicate register offset and shift mask header files as well. Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-07-01drm/amd/pm: skip PrepareMp1ForUnload message in s0ixShyam Sundar S K1-1/+2
The documentation around PrepareMp1ForUnload message says that anything sent to SMU after this command would be stalled as the PMFW would not be in a state to take further job requests. Technically this is right in case of S3 scenario. But, this might not be the case during s0ix as the PMC driver would be the last to send the SMU on the OS_HINT. If SMU gets a PrepareMp1ForUnload message before the OS_HINT, this would stall the entire S0ix process. Results show that, this message to SMU is not required during S0ix and hence skip it. Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-30amdgpu/pm: remove code duplication in show_power_cap callsDarren Powell1-74/+21
v3: updated patch to apply to latest code v2: reorder to check pointers before calling pm_runtime_* functions created generic function and call with enum from * amdgpu_hwmon_show_power_cap_max * amdgpu_hwmon_show_power_cap * amdgpu_hwmon_show_power_cap_default === Test === AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 10` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} cp pp_show_power_cap.txt{,.old} lspci -nn | grep "VGA\|Display" > pp_show_power_cap.test.log FILES=" power1_cap power1_cap_max power1_cap_default " for f in $FILES do echo $f = `cat $HWMON_DIR/$f` >> pp_show_power_cap.test.log done Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-29drm/amdgpu: Power down VCN and JPEG before disabling SMU featuresChengzhe Liu1-2/+6
When unloading driver, if VCN is powered on, sending message DisableAllSmuFeatures to SMU will cause SMU hang. We need to power down VCN and JPEG before clean up SMU. Signed-off-by: Chengzhe Liu <ChengZhe.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-18drm/amd/pm: Disable SMU messages in navi10 sriovYifan Zha1-4/+4
[Why] sriov vf send unsupported SMU message lead to fail. [How] disable related messages in sriov. Signed-off-by: Yifan Zha <Yifan.Zha@amd.com> Acked-by: Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by: Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-18drm/amdgpu: message smu to update hbm bad page numberStanley.Yang2-0/+21
Use SMU to update the bad pages rather than directly accessing the EEPROM from the driver. Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-18amdgpu/pm: replaced snprintf usage in amdgpu_pm.c with sysfs_emitDarren Powell1-13/+14
replaced snprintf usage in amdgpu_pm.c with sysfs_emit fixed warning on comparing int with uint32_t in amdgpu_get_pp_num_states() == Test == AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 10` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" > scnprintf.test.log FILES="pp_num_states pp_od_clk_voltage pp_features pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_vclk pp_dpm_dclk pp_dpm_dcefclk pp_power_profile_mode " for f in $FILES do echo === $f === >> scnprintf.test.log cat $HWMON_DIR/device/$f >> scnprintf.test.log done Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-11drm/amd/pm: support ss metrics read on yellow_carpSathishkumar S1-0/+34
add support to read smart shift apu and dgpu power share on yellow_carp Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-11drm/amd/pm: support ss metrics read on renoirSathishkumar S1-0/+34
add support to read smart shift apu and dgpu power share on renoir. Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-11drm/amd/pm: Only primary die supports power dataLijo Lazar1-11/+46
On aldebaran, only primary die fetches valid power data. Show power/energy values as 0 on secondary die. Also, power limit should not be set through secondary die. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-11drm/amd/pm: correct the power limits reporting on OOB supportedEvan Quan8-35/+95
As OOB(out-of-band) interface may be used to update the power limits. Thus to make sure the power limits reporting of our driver always reflects the correct values, the internal cache must be aligned carefully. V2: add support for out-of-band of other ASICs align cached current power limit with OOB imposed Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-By: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-11drm/amd/pm: correct the dpm features disablement for Navi1xEvan Quan1-1/+2
For BACO scenario, PMFW will handle the dpm features disablement and interaction with RLC properly. Driver involvement is unnecessary and error prone. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-11drm/amd/pm: update the cached dpm feature statusEvan Quan5-13/+50
For some ASICs, the real dpm feature disablement job is handled by PMFW during baco reset and custom pptable loading. Cached dpm feature status need to be updated to pair that. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-11drm/amd/pm: correct the runpm handling for BACO supported ASICEvan Quan4-13/+55
Via the fSMC_MSG_ArmD3 message, PMFW can properly act on the Dstate change. Driver involvement for determining the timing for BACO enter/exit is not needed. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-11drm/amd/pm: drop the incomplete fix for Navi14 runpm issueEvan Quan1-25/+1
As the fix by adding PPSMC_MSG_PrepareMp1ForUnload is proved to be incomplete. Another fix(see link below) has been sent out. Link: https://lore.kernel.org/linux-pci/20210602021255.939090-1-evan.quan@amd.com/ Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-10drm/amd/pm: Add aldebaran throttler translationGraham Sider1-5/+22
Perform dependent to independent throttle status translation for aldebaran. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-10drm/amd/pm: Add renoir throttler translationGraham Sider1-5/+24
Perform dependent to independent throttle status translation for renoir. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-10drm/amd/pm: Add vangogh throttler translationGraham Sider1-9/+29
Perform dependent to independent throttle status translation for vangogh. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-10drm/amd/pm: Add sienna cichlid throttler translationGraham Sider1-5/+29
Perform dependent to independent throttle status translation for sienna cichlid. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-10drm/amd/pm: Add navi1x throttler translationGraham Sider1-0/+34
Perform dependent to independent throttle status translation for navi1x. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-10drm/amd/pm: Add arcturus throttler translationGraham Sider1-5/+28
Perform dependent to independent throttle status translation for arcturus. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-10drm/amd/pm: Add common throttler translation funcGraham Sider2-0/+17
Defines smu_cmn_get_indep_throttler_status which performs ASIC independent translation given a corresponding lookup table. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-10drm/amd/pm: Add ASIC independent throttle bitsGraham Sider1-0/+42
Add new defines for thermal throttle status bits which are ASIC independent. This bit field will be visible to userspace via gpu_metrics alongside the previous ASIC dependent bit fields. Seperated into four types: power throttlers (16 bits), current throttlers (16 bits), temperature (24 bits), other (8 bits). Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-10drm/amd/pm: Add u64 throttler status field to gpu_metricsGraham Sider1-0/+3
This patch set adds support for a new ASIC independant u64 throttler status field (indep_throttle_status). Piggybacks off the gpu_metrics_v1_3 bump and similarly bumps gpu_metrics_v2 version (to v2_2) to add field. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-08drm/amd/pm: fix warning reported by kernel test robotXiaomeng Hou1-1/+1
Kernel test robot throws warning -> >> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:483:2: warning: variable 'member_type' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized] default: ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:487:47: note: uninitialized use occurs here return yellow_carp_get_smu_metrics_data(smu, member_type, value); ^~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.c:465:2: note: variable 'member_type' is declared here MetricsMember_t member_type; ^ 1 warning generated. Fix this warning by return errno when the clk type is unsupported. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-08amdgpu/pm: add kernel documentation for smu_get_power_limitDarren Powell1-0/+10
added doc tag "amdgpu_pp_power" with description added tags for enums pp_power_limit_level, pp_power_type added tag for function smu_get_power_limit Test: * Temporary insertion into Documentation/gpu/amdgpu.rst ------------START------------ Power Limit ----------- .. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h :doc: amdgpu_pp_power .. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h :identifiers: pp_power_limit_level .. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h :identifiers: pp_power_type .. kernel-doc:: drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c :identifiers: smu_get_power_limit -------------END------------- Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-08amdgpu/pm: handle return value for get_power_limitDarren Powell1-15/+24
Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-08amdgpu/pm: modify and add smu_get_power_limit to Powerplay APIDarren Powell3-17/+7
modify args of smu_get_power_limit to match Powerplay API .get_power_limit add smu_get_power_limit to Powerplay API swsmu_pm_funcs remove special handling of smu in amdgpu_hwmon_show_power_cap* * Test AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" ; \ echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ; \ echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ; \ echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-08amdgpu/pm: modify Powerplay API get_power_limit to use new pp_power enumsDarren Powell2-22/+38
updated {amd_pm_funcs}->get_power_limit() signature rewrote pp_get_power_limit to use new enums pp_get_power_limit now returns -EOPNOTSUPP for unknown power limit update calls to {amd_pm_funcs}->get_power_limit() * Test Notes * testing hardware was NAVI10 (tests SMU path) ** needs testing on VANGOGH ** needs testing on SMU < 11 ** ie, one of TOPAZ, FIJI, TONGA, POLARIS10, POLARIS11, POLARIS12, VEGAM, CARRIZO, STONEY, VEGA10, VEGA12,VEGA20, RAVEN, BONAIRE, HAWAII * Test AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" ; \ echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ; \ echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ; \ echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-08amdgpu/pm: clean up smu_get_power_limit function signatureDarren Powell3-12/+43
add two new powerplay enums (limit_level, type) add enums to smu_get_power_limit signature remove input bitfield stuffing of output variable limit update calls to smu_get_power_limit * Test AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} lspci -nn | grep "VGA\|Display" ; \ echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ; \ echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ; \ echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-08amdgpu/pm: reorder definition of swsmu_pm_funcs for readabilityDarren Powell1-24/+24
Match the order of definition to the structure's declaration to help with locating included and missing functions of the API Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amd/pm: disable manually setting MCLK power level on yellow carpXiaomeng Hou1-12/+10
PMFW provides specific messages for setting fclk freq range thus adjust the power level. There's misusing of these messages when setting dpm mclk. Since actually mclk could adjust automatically complying with fclk, remove standalone support for mclk dpm level setting. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amdgpu: add mode2 reset support for yellow carpAaron Liu1-0/+26
This patch adds mode2 reset support for yellow carp. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amd/pm: add set_performance_level function for yellow carpXiaomeng Hou1-0/+84
This patch enables editing sysfs file power_dpm_force_performance_level for yellow carp. User could thus adjust the dpm forced level. v2: enable fine grain control of GFXCLK only when in manual performance level mode. In other mode, the min/max range of GFXCLK will be reset to corresponding values. Ex: To enable min 300MHz / max 600MHz gfx clocks 1) echo manual > /sys/bus/pci/devices/.../power_dpm_force_performance_level 2) echo s 0 300 > /sys/bus/pci/devices/.../pp_od_clk_voltage 3) echo s 1 600 > /sys/bus/pci/devices/.../pp_od_clk_voltage 4) echo c > /sys/bus/pci/devices/.../pp_od_clk_voltage Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amd/pm: add the interface to dump smu metrics table for yellow carpXiaomeng Hou1-1/+55
This patch is to add the interface to dump smu metrics table for yellow carp. Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amd/pm: add callbacks to read/write sysfs file pp_power_profile_modeXiaomeng Hou1-0/+86
Implement the sysfs API for getting/setting pp_power_profile_mode for yellow carp. Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amd/pm: add callback get_dpm_ultimate_freq for yellow carpXiaomeng Hou1-0/+111
Add callback function to get the hard frequency range of a clock domain for yellow carp. Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amd/pm: add callback to get bootup values for yellow carpXiaomeng Hou3-0/+139
Add get_vbios_bootup_values function to get the bootup values for yellow carp. Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amd/pm: add PrepareMp1ForUnload support for yellow carpAaron Liu1-0/+4
Driver needs to notify the PMFW when the RLC is disabled. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amd/pm: add callback force_clk_levels for yellow carpXiaomeng Hou1-0/+114
Implement the sysfs API to set a range of allowed DPM levels for specific clock domain. v2: return error directly if the specified clock type not supported Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amd/pm: initialize feature_enabled/feature_support bitmap for yellow carpXiaomeng Hou1-0/+25
Initialize the feature_enabled and feature_supported bitmap for yellow carp. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amd/pm: implement is_dpm_running() callback for yellow carpXiaomeng Hou1-9/+21
Implement function to check if DPM is running for yellow carp. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amd/pm: add feature map for yellow carpXiaomeng Hou1-0/+42
Add feature map for yellow carp. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amd/pm: add support to get dpm clock value for yellow carpXiaomeng Hou1-1/+127
Implement the sysfs API for getting values of pp dpm clocks(pp_dpm_socclk/mclk/fclk/vclk/dclk) for yellow carp. Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amd/pm: add the fine grain tuning function for yellow carpXiaomeng Hou1-0/+116
Use the pp_od_clk_voltage sysfs file to configure the min and max value of gfx clock frequency or to restore the default values. Command guide: echo "s level value" > pp_od_clk_voltage "s" - set the sclk frequency "level" - 0 or 1, "0" represents the min value, "1" represents the max value "value" - the target value of sclk frequency, it should be limited in the safe range echo "r" > pp_od_clk_voltage "r" - reset the sclk frequency, restore the default value echo "c" > pp_od_clk_voltage "c" - commit the min and max value of sclk frequency to the system only after the commit command, the setting target values by "s" command will take effect Example: 1) check the default sclk frequency $ cat pp_od_clk_voltage OD_SCLK: 0: 200Mhz 1: 600Mhz OD_RANGE: SCLK: 200MHz 600MHz 2) use "s" -- set command to configure the min or max sclk frequency $ echo "s 0 300" > pp_od_clk_voltage $ echo "s 1 500" > pp_od_clk_voltage $ echo "c" > pp_od_clk_voltage $ cat pp_od_clk_voltage OD_SCLK: 0: 300Mhz 1: 500Mhz OD_RANGE: SCLK: 200MHz 600MHz 3) use "r" -- reset command to restore the min and max sclk frequency $ echo "r" > pp_od_clk_voltage $ echo "c" > pp_od_clk_voltage $ cat pp_od_clk_voltage OD_SCLK: 0: 200Mhz 1: 600Mhz OD_RANGE: SCLK: 200MHz 600MHz v2: modify the description of reset command usage - need to do "commit" after set the restore command Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amd/pm: add set_watermarks_table function for yellow carpXiaomeng Hou1-0/+61
Add callback function set_watermarks_table for yellow carp. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amd/pm: add read_sensor function for yellow carpXiaomeng Hou1-0/+140
Add callback function read_sensor for yellow carp. Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-04drm/amdgpu/pm: support smu_post_init for yellow carpAaron Liu1-3/+3
Add smu_post_init support for yellow carp. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-09 13:23:02 +0000