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path: root/drivers/gpio/gpio-aspeed.c
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2017-12-28gpio: fix aspeed_gpio_banks array size checkVasyl Gomonovych1-1/+1
The test should be >= ARRAY_SIZE() instead of > ARRAY_SIZE(). Signed-off-by: Vasyl Gomonovych <gomonovych@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-12-02gpio: aspeed: Add support for reset toleranceAndrew Jeffery1-2/+37
Use the new pinconf parameter for state persistence to expose the associated capability of the Aspeed GPIO controller. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-09Merge branch 'gpio-irqchip-rework' of /home/linus/linux-gpio into develLinus Walleij1-3/+6
2017-11-08gpio: Move irq_valid_mask into struct gpio_irq_chipThierry Reding1-2/+2
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-08gpio: Move irqdomain into struct gpio_irq_chipThierry Reding1-1/+1
In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-10-19gpio: mark expected switch fall-throughsGustavo A. R. Silva1-0/+3
In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-09-22pinctrl/gpio: Unify namespace for cross-callsLinus Walleij1-2/+2
The pinctrl_request_gpio() and pinctrl_free_gpio() break the nice namespacing in the other cross-calls like pinctrl_gpio_foo(). Just rename them and all references so we have one namespace with all cross-calls under pinctrl_gpio_*(). Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-08-15gpio: aspeed: Remove reference to clock name in debounce warning messageAndrew Jeffery1-1/+1
HPLL is in fact not the clock we need. Remove the description of which clock we failed to find a phandle to in order to avoid any further error. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-05-22gpio: aspeed: Don't attempt to debounce if disabledJoel Stanley1-0/+3
We warn the user at driver probe time that debouncing is disabled. However, if they request debouncing later on we print a confusing error message: gpio_aspeed 1e780000.gpio: Failed to convert 5000us to cycles at 0Hz: -524 Instead bail out when the clock is not present. Fixes: 5ae4cb94b3133 (gpio: aspeed: Add debounce support) Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24gpio: aspeed: Add open-source and open-drain supportAndrew Jeffery1-0/+4
As per the datasheet, manage the IO and value states to implement open-source/open-drain, but do this by falling back to gpiolib's emulation. This commit simply makes the behaviour explicit for clarity, rather than relying on the implicit return of -ENOTSUPP to trigger the emulation. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24gpio: aspeed: Add debounce supportAndrew Jeffery1-5/+276
Each GPIO in the Aspeed GPIO controller can choose one of four input debounce states: to disable debouncing for an input, or select from one of three programmable debounce timer values. Each GPIO in a four-bank-set is assigned one bit in each of two debounce configuration registers dedicated to the set, and selects a debounce state by configuring the two bits to select one of the four options. The limitation on debounce timer values is managed by mapping offsets onto a configured timer value and keeping count of the number of users a timer has. Timer values are configured on a first-come-first-served basis. A small twist in the hardware design is that the debounce configuration register numbering is reversed with respect to the binary representation of the debounce timer of interest (i.e. debounce register 1 represents bit 1, and debounce register 2 represents bit 0 of the timer numbering). Tested on an AST2500EVB with additional inspection under QEMU's romulus-bmc machine. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-02-04gpio: aspeed: Remove dependence on GPIOF_* macrosAndrew Jeffery1-3/+2
1736f75d35e47409ad776273133d0f558a4c8253 is a (v2) patch which had unresolved review comments[1]. Address the comments by removing the use of macros from the consumer header (this patch represents the diff between v2 and v3[2]). [1] https://lkml.org/lkml/2017/1/26/337 [2] https://lkml.org/lkml/2017/1/26/786 Fixes: 1736f75d35e4 ("gpio: aspeed: Add banks Y, Z, AA, AB and AC") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-26gpio: aspeed: Add banks Y, Z, AA, AB and ACAndrew Jeffery1-14/+160
This is less straight-forward than one would hope, as some banks only have 4 pins rather than 8, others are output only, yet more (W and X, already supported) are input-only, and in the case of the g4 SoC bank AC doesn't exist. Add some structs to describe the varying properties of different banks and integrate mechanisms to deny requests for unsupported configurations. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-01-26gpio: aspeed: Make bank names stringsJoel Stanley1-7/+7
The Aspeed SoCs have more GPIOs than can be represented with A-Z. The documentation uses two letter names such as AA and AB, so make the names a three-character array in the bank struct to accommodate this. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-23gpio: aspeed: remove redundant return value checkWei Yongjun1-3/+0
Remove unneeded error handling on the result of a call to platform_get_resource() when the value is passed to devm_ioremap_resource(). Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-15gpio: aspeed: fix return value check in aspeed_gpio_probe()Wei Yongjun1-2/+2
In case of error, the function devm_ioremap_resource() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Acked-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-13gpio: aspeed: add MODULE_LICENSE()Linus Walleij1-0/+1
The build complains about missing MODULE_LICENSE() in the Aspeed GPIO driver. The license is evident from the file header, put in "GPL". Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Alistair Popple <alistair@popple.id.au> Cc: Jeremy Kerr <jk@ozlabs.org> Cc: Andrew Jeffery <andrew@aj.id.au> Acked-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-09-07gpio: Add Aspeed driverJoel Stanley1-0/+457
The Aspeed SoCs contain GPIOs banked by letter, where each bank contains 8 pins. The GPIO banks are then grouped in sets of four in the register layout. The implementation exposes multiple banks through the one driver and requests and releases pins via the pinctrl subsystem. The hardware supports generation of interrupts from all GPIO-capable pins. A number of hardware features are not yet supported: Configuration of interrupt direction (ARM or LPC), debouncing, and WDT reset tolerance for output ports. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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