linux - Linux Kernel (branches are rebased on master from time to time)

Age	Commit message (Collapse)	Author	Files	Lines
2011-09-13	locking, dma, ipu: Annotate bank_lock as raw	Uwe Kleine-König	1	-24/+24
	The bank_lock can be taken in atomic context (irq handling) and therefore cannot be preempted on -rt - annotate it. In mainline this change documents the low level nature of the lock - otherwise there's no functional difference. Lockdep and Sparse checking will work as usual. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Cc: kernel@pengutronix.de Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Cc: Dan Williams <dan.j.williams@intel.com> Link: http://lkml.kernel.org/r/1311949627-13260-1-git-send-email-u.kleine-koenig@pengutronix.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-03-25	dma: Ipu: Convert interupt code	Thomas Gleixner	1	-29/+29
	Convert to the new irq chip functions and cleanup the name space. [ Guennadi reported: irq_data_get_chip_data is undefined. Yes, I screwed up. it needs to be irq_data_get_irq_chip_data ] Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Cc: Dan Williams <dan.j.williams@intel.com> LKML-Reference: <alpine.LFD.2.00.1103251220000.31464@localhost6.localdomain6>
2009-03-25	dma: improve section assignment in i.MX31 IPU DMA driver	Guennadi Liakhovetski	1	-1/+1
	The i.MX31 IPU DMA driver is a platform driver, but doesn't need hotplug, so we can use __init and __exit function attributes. Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-01-19	i.MX31: Image Processing Unit DMA and IRQ drivers	Guennadi Liakhovetski	1	-0/+413
	i.MX3x SoCs contain an Image Processing Unit, consisting of a Control Module (CM), Display Interface (DI), Synchronous Display Controller (SDC), Asynchronous Display Controller (ADC), Image Converter (IC), Post-Filter (PF), Camera Sensor Interface (CSI), and an Image DMA Controller (IDMAC). CM contains, among other blocks, an Interrupt Generator (IG) and a Clock and Reset Control Unit (CRCU). This driver serves IDMAC and IG. They are supported over dmaengine and irq-chip APIs respectively. IDMAC is a specialised DMA controller, its DMA channels cannot be used for general-purpose operations, even though it might be possible to configure a memory-to-memory channel for memcpy operation. This driver will not work with generic dmaengine clients, clients, wishing to use it must use respective wrapper structures, they also must specify which channels they require, as channels are hard-wired to specific IPU functions. Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Guennadi Liakhovetski <lg@denx.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>