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path: root/drivers/cxl
AgeCommit message (Expand)AuthorFilesLines
2022-02-08cxl/pci: Store component register base in cxldsBen Widawsky2-0/+14
2022-02-08cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams7-24/+24
2022-02-08cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky8-29/+108
2022-02-08cxl/core: Emit modalias for CXL devicesDan Williams1-9/+17
2022-02-08cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams8-49/+348
2022-02-08cxl/core: Generalize dport enumeration in the coreDan Williams6-110/+167
2022-02-08cxl/pci: Rename pci.h to cxlpci.hDan Williams4-3/+4
2022-02-08cxl/port: Up-level cxl_add_dport() locking requirements to the callerDan Williams2-2/+3
2022-02-08cxl/pmem: Introduce a find_cxl_root() helperDan Williams3-4/+60
2022-02-08cxl/port: Introduce cxl_port_to_pci_bus()Dan Williams3-5/+49
2022-02-08cxl/core/port: Use dedicated lock for decoder target listDan Williams2-7/+25
2022-02-08cxl: Prove CXL lockingDan Williams5-24/+130
2022-02-08cxl/core: Track port depthBen Widawsky2-0/+4
2022-02-08cxl/core/port: Make passthrough decoder init implicitBen Widawsky2-6/+8
2022-02-08cxl/core: Fix cxl_probe_component_regs() error messageDan Williams1-1/+1
2022-02-08cxl/core/port: Clarify decoder creationBen Widawsky3-11/+92
2022-02-08cxl/core: Convert decoder range to resourceBen Widawsky3-18/+35
2022-02-08cxl/decoder: Hide physical address information from non-rootDan Williams1-1/+1
2022-02-08cxl/core/port: Rename bus.c to port.cDan Williams2-1/+1
2022-02-08cxl: Introduce module_cxl_driverBen Widawsky1-0/+3
2022-02-08cxl/acpi: Map component registers for Root PortsBen Widawsky5-54/+80
2022-02-08cxl/pci: Add new DVSEC definitionsBen Widawsky1-0/+15
2022-02-08cxl: Flesh out register namesBen Widawsky2-16/+17
2022-02-08cxl/pci: Defer mailbox status checks to command timeoutsDan Williams1-101/+33
2022-02-08cxl/pci: Implement Interface Ready TimeoutBen Widawsky1-0/+35
2022-02-08cxl: Rename CXL_MEM to CXL_PCIBen Widawsky2-12/+13
2022-01-04cxl/core: Remove cxld_const_init in cxl_decoder_alloc()Nathan Chancellor2-5/+3
2021-11-15cxl/pmem: Fix module reload vs workqueue stateDan Williams3-3/+42
2021-11-15ACPI: NUMA: Add a node and memblk for each CFMWS not in SRATAlison Schofield1-1/+2
2021-11-15cxl/test: Mock acpi_table_parse_cedt()Dan Williams1-0/+2
2021-11-15cxl/acpi: Convert CFMWS parsing to ACPI sub-table helpersDan Williams2-147/+88
2021-11-15cxl/memdev: Remove unused cxlmd fieldIra Weiny1-2/+0
2021-11-15cxl/core: Convert to EXPORT_SYMBOL_NS_GPLDan Williams6-29/+29
2021-11-15cxl/memdev: Change cxl_mem to a more descriptive nameIra Weiny5-211/+214
2021-11-15cxl/mbox: Remove bad commentIra Weiny1-2/+0
2021-11-15cxl/pmem: Fix reference counting for delayed workDan Williams1-4/+13
2021-11-08Merge tag 'cxl-for-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds12-1311/+1580
2021-10-29cxl/pci: Use pci core's DVSEC functionalityBen Widawsky1-24/+2
2021-10-29cxl/pci: Split cxl_pci_setup_regs()Ben Widawsky1-36/+37
2021-10-29cxl/pci: Add @base to cxl_register_mapDan Williams2-15/+26
2021-10-29cxl/pci: Make more use of cxl_register_mapBen Widawsky1-34/+25
2021-10-29cxl/pci: Remove pci request/release regionsBen Widawsky1-5/+0
2021-10-29cxl/pci: Fix NULL vs ERR_PTR confusionDan Williams1-1/+1
2021-10-29cxl/pci: Remove dev_dbg for unknown register blocksBen Widawsky1-3/+0
2021-10-29cxl/pci: Convert register block identifiers to an enumBen Widawsky1-6/+8
2021-10-08cxl/acpi: Do not fail cxl_acpi_probe() based on a missing CHBSAlison Schofield1-4/+6
2021-09-25cxl/core: Replace unions with struct_group()Kees Cook1-43/+18
2021-09-21cxl/pci: Disambiguate cxl_pci further from cxl_memBen Widawsky1-33/+35
2021-09-21cxl/core: Split decoder setup into alloc + addDan Williams5-126/+114
2021-09-21tools/testing/cxl: Introduce a mock memory device + driverDan Williams3-5/+5
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