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path: root/drivers/cxl/core
AgeCommit message (Expand)AuthorFilesLines
2022-03-22cxl/core/port: Fix NULL but dereferenced coccicheck errorWan Jiabing1-1/+4
2022-02-17cxl/port: Hold port reference until decoder releaseDan Williams1-0/+4
2022-02-17cxl/port: Fix endpoint refcount leakDan Williams1-1/+2
2022-02-11cxl/core: Fix cxl_device_lock() class detectionDan Williams1-1/+1
2022-02-11cxl/core/port: Fix unregister_port() lock assertionDan Williams1-4/+20
2022-02-08cxl/regs: Fix size of CXL Capability Header RegisterJonathan Cameron1-2/+2
2022-02-08cxl/core/port: Handle invalid decodersDan Williams1-6/+30
2022-02-08cxl/core/port: Fix / relax decoder target enumerationDan Williams1-1/+4
2022-02-08cxl/core/port: Add endpoint decodersBen Widawsky2-8/+63
2022-02-08cxl/core: Move target_list out of base decoder attributesDan Williams1-1/+2
2022-02-08cxl/mem: Add the cxl_mem driverBen Widawsky2-4/+117
2022-02-08cxl/core/port: Add switch port enumerationDan Williams1-9/+418
2022-02-08cxl/memdev: Add numa_node attributeDan Williams1-0/+17
2022-02-08cxl/pci: Emit device serial numberDan Williams1-0/+11
2022-02-08cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams3-14/+14
2022-02-08cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky2-4/+32
2022-02-08cxl/core: Emit modalias for CXL devicesDan Williams1-9/+17
2022-02-08cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams5-15/+298
2022-02-08cxl/core: Generalize dport enumeration in the coreDan Williams3-39/+154
2022-02-08cxl/pci: Rename pci.h to cxlpci.hDan Williams1-1/+1
2022-02-08cxl/port: Up-level cxl_add_dport() locking requirements to the callerDan Williams1-2/+1
2022-02-08cxl/pmem: Introduce a find_cxl_root() helperDan Williams2-4/+59
2022-02-08cxl/port: Introduce cxl_port_to_pci_bus()Dan Williams1-0/+37
2022-02-08cxl/core/port: Use dedicated lock for decoder target listDan Williams1-7/+23
2022-02-08cxl: Prove CXL lockingDan Williams2-13/+38
2022-02-08cxl/core: Track port depthBen Widawsky1-0/+2
2022-02-08cxl/core/port: Make passthrough decoder init implicitBen Widawsky1-1/+8
2022-02-08cxl/core: Fix cxl_probe_component_regs() error messageDan Williams1-1/+1
2022-02-08cxl/core/port: Clarify decoder creationBen Widawsky1-8/+75
2022-02-08cxl/core: Convert decoder range to resourceBen Widawsky1-2/+21
2022-02-08cxl/decoder: Hide physical address information from non-rootDan Williams1-1/+1
2022-02-08cxl/core/port: Rename bus.c to port.cDan Williams2-1/+1
2022-02-08cxl/acpi: Map component registers for Root PortsBen Widawsky1-0/+56
2022-01-04cxl/core: Remove cxld_const_init in cxl_decoder_alloc()Nathan Chancellor1-4/+2
2021-11-15cxl/pmem: Fix module reload vs workqueue stateDan Williams1-1/+7
2021-11-15cxl/core: Convert to EXPORT_SYMBOL_NS_GPLDan Williams6-29/+29
2021-11-15cxl/memdev: Change cxl_mem to a more descriptive nameIra Weiny2-116/+115
2021-11-15cxl/mbox: Remove bad commentIra Weiny1-2/+0
2021-09-21cxl/core: Split decoder setup into alloc + addDan Williams3-93/+48
2021-09-21tools/testing/cxl: Introduce a mock memory device + driverDan Williams1-3/+3
2021-09-21cxl/mbox: Move command definitions to common locationDan Williams1-39/+6
2021-09-21cxl/bus: Populate the target list at decoder createDan Williams1-11/+69
2021-09-21cxl/pmem: Add support for multiple nvdimm-bridge objectsDan Williams1-1/+31
2021-09-21cxl/mbox: Add exclusive kernel command supportDan Williams2-0/+37
2021-09-21cxl/mbox: Convert 'enabled_cmds' to DECLARE_BITMAPDan Williams1-11/+1
2021-09-21cxl/mbox: Move mailbox and other non-PCI specific infrastructure to the coreDan Williams5-9/+910
2021-09-21cxl/pci: Make 'struct cxl_mem' device type genericDan Williams1-4/+3
2021-09-09Merge tag 'cxl-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds6-0/+1413
2021-09-07cxl/registers: Fix Documentation warningDan Williams1-1/+14
2021-09-07cxl/pmem: Fix Documentation warningDan Williams1-2/+28
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